UPD301B/C

DS00003412A-page 28

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2020 Microchip Technology Inc.

4.5.1

PD MAC TRANSMITTER

The PD MAC transmitter is comprised of three major blocks:

•

TX Queue:

The TX Queue is where software loads the message to be transmitted.

•

TX Control:

The TX Control implements the necessary control logic. It is responsible for reading the data from the TX queue

and based on the data processing mode (automatic or raw), processing the data to make it suitable (nibbles with

control information) for use by the TX Comm. It is also responsible for generating packet framing and terminating

the packet in automatic mode, and generating messages for automatic response (GoodCRC and BIST Error

Count). TX Control also handles the selection of the SOP type that is to be transmitted.

•

TX Comm:

The TX Comm is comprised of a TX CRC generator, a 4b5b encoder, serializer, preamble generator, and TX bit

timer. It takes the nibble data, computes and inserts the CRC, 5b encodes, and generates the baseband serial

data. Preamble insertion is also performed by this logic.

4.5.2

PD MAC RECEIVER

The PD MAC receiver is comprised of three major blocks:

•

RX Queue:

The RX Queue is where software reads the received messages.

•

RX Control:

The RX Control implements the necessary control logic. It is responsible for validating the received packet, updat-

ing the RX Queue status, and triggering automatic responses, if required.

•

RX Comm:

The RX Comm is comprised of the Clock and Data Recovery (CDR), RX DES (de-serializer) (serial-to-parallel

converter, 4b5b decoder, and framing detector), RX CRC32 (CRC calculator, receive timer), and other logic to

detect valid packet reception.

4.5.3

PD MAC BIST

The PD MAC incorporates BIST functions as defined in the USB PD Specification. It is comprised of a TX and RX block.

The BIST TX block contains a PRBS (Pseudo Random Binary Sequence) generator, BIST pattern generation logic, and

its own bit-timing logic. The SOP type used by TX BIST Test Frames is a 20-bit static vector which is created by multi-

plexing between the five SOP ordered sets based on a register setting. The resultant 20-bit vector is simply bit selected

when the packet is transmitted.

The BIST RX block contains a PRBS generator and bit error detection logic. BIST RX is used only during the BIST

Receiver Test.

4.6

Supported Power Delivery (PD) Functionality

4.6.1

SUPPORTED PD MESSAGES

The UPD301B/C is capable of supporting the USB PD Control messages defined within the.USB Power Delivery 3.0

Specification. The complete list of supported messages depends on the release version of the USB Power Delivery Soft-

ware Framework (PSF). The minimum set of supported features are:

• GoodCRC

• Accept

• Reject

• Ping

• PS_RDY

• Get_Source_Cap (Sink Role only)

• Get_Sink_Cap (Source Role only)

• VCONN_Swap

• Wait

• Soft_Reset