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VT8601 Datasheet(PDF) 25 Page - List of Unclassifed Manufacturers

Part # VT8601
Description  Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller
PDF  144 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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VT8601 Datasheet(HTML) 25 Page - List of Unclassifed Manufacturers

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VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-19-
Pinouts
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CRT Interface
Signal Name
Pin #
I/O
Signal Description
RED
C2
A
Red. Red analog output to the CRT. Connect 75
Ω load resistor to GNDR (RGB Return)
and connect to VGA connector through a series ferrite bead and 10pF capacitors to GNDR
on both input and output sides of the bead (see “Apollo ProMedia Design Guide”).
GRN
D3
A
Green. Green analog output to the CRT. Connect same as RED.
BLUE
D2
A
Blue. Blue analog output to the CRT. Connect same as RED.
HSYNC
E2
O
Horizontal Sync. Digital horizontal sync output to the CRT. Also used (with VSYNC)
to signal power management state information to the CRT per the VESA™ DPMS™
standard. Connect to VGA connector through a series 47
Ω resistor and 120pF capacitor
to ground (see “Apollo ProMedia Design Guide”).
VSYNC
E1
O
Vertical Sync. Digital vertical sync output to the CRT. Also used (with HSYNC) to
signal power management state information to the CRT per the VESA™ DPMS™
standard. Connect to VGA connector through a series 47
Ω resistor and 120pF capacitor
to ground (see “Apollo ProMedia Design Guide”).
SDA
F2
IO
DDC Data/Address. Serial I
2C protocol for VESA™ DDC2B signaling to the CRT.
Connect this pin to VCC5 through a 4.7K
Ω pullup. Connect to the VGA connector only
(pin 12 of the connector). Connect through a ferrite bead and 120pF capacitor to ground
(on the output side of the bead).
Refer to the “Apollo ProMedia Design Guide” for
additional information.
SCL
F3
IO
DDC Clock. Serial I
2C protocol for VESA™ DDC2B signaling to the CRT. Connect this
pin to VCC5 through a 4.7K
Ω pullup. Connect to the VGA connector only (pin 15 of the
VGA connector). Connect through a ferrite bead and 120pF capacitor to ground (on the
output side of the bead). Refer to the “Apollo ProMedia Design Guide” for additional
information.
DFP Interface
Signal Name
Pin #
I/O
Signal Description
PD[23-0]
(see pin list)
O
Panel Data. Digital pixel data outputs to the panel.
SCLK
G4
O
Shift Clock. Clock for transferring digital pixel data.
DE
H3
O
Data Enable. Indicates valid data on PD[23-0].
LP
G5
O
Line Pulse. Digital monitor equivalent of HSYNC.
FLM
G3
O
First Line Marker. Digital monitor equivalent of VSYNC.
EVDD
F1
O
Enable Panel VDD Power.
EVEE
H5
O
Enable Panel VEE Power.
EBLT
G1
O
Enable Panel Backlight.
Note: Connect SHFCLK, DE, LP, and FLM to external TMDS transmitters through series 22
Ω resistors. See the “Apollo
ProMedia Design Guide” for DFP interface design examples and additional information.



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