VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-45-
Device 0 Bus 0 Host Bridge Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 0 Offset 72 - CPU to PCI Flow Control 2.........RWC
7
Retry Status
0
Retry occurred less than retry limit ........default
1
Retry occurred more than x times (where x is
defined by bits 5-4) ................. write 1 to clear
6
Retry Timeout Action
0
Retry Forever (record status only)..........default
1
Flush buffer for write or return all 1s for read
5-4
Retry Limit
00 Retry 2 times ..........................................default
01 Retry 16 times
10 Retry 4 times
11 Retry 64 times
3
Clear Failed Data and Continue Retry
0
Flush the entire post-write buffer ...........default
1
When data is posting and master (or target)
abort fails, pop the failed data if any, and keep
posting
2
CPU Backoff on PCI Read Retry Failure
0
Disable ...................................................default
1
Backoff CPU when reading data from PCI and
retry fails
1
Reduce 1T for FRAME# Generation
0
Disable ...................................................default
1Enable
0
Reduce 1T for CPU Read of PCI Slave
0
Disable ..................................................Default
1
Enable
Device 0 Offset 73 - PCI Master Control 1..................... RW
7
Reserved
........................................ always reads 0
6
PCI Master 1-Wait-State Write
0
Zero wait state TRDY# response........... default
1
One wait state TRDY# response
5
PCI Master 1-Wait-State Read
0
Zero wait state TRDY# response........... default
1
One wait state TRDY# response
4
Disable Prefetch when Doing Delay Transaction
0
Enable .................................................... default
1
Disable
3
Assert STOP# after PCI Master Write Timeout
0
Disable................................................... default
1Enable
2
Assert STOP# after PCI Master Read Timeout
0
Disable................................................... default
1Enable
1
LOCK# Function
0
Disable................................................... default
1Enable
0
PCI Master Broken Timer Enable
0
Disable................................................... default
1
Enable. Force into arbitration when there is no
FRAME# 16 PCICLK’s after the grant. Does
not apply to south bridge PREQ# input
Device 0 Offset 74 - PCI Master Control 2..................... RW
7
PCI Master Read Prefetch by Enhance Command
0
Always Prefetch ..................................... default
1
Prefetch only if Enhance command
6
PCI Master Write Merge
0
Disable................................................... default
1Enable
5
Reserved
........................................ always reads 0
4
Dummy Request Handling............Should be set to 1
0
As VP3................................................... default
1
Complete Fix
3
PCI Delay Transaction Time-Out
0
Disable................................................... default
1Enable
2
Backoff CPU Immediately on CPU to AGP Retry
0
Disable................................................... default
1Enable
1-0
CPU/PCI Master Latency Timer Control
00 AGP Master Reloads MLT timer........... default
01 Falling edge of AGP Master Request reloads
MLT timer
10 Rising Edge of AGP Master Request clears
MLT timer and falling edge reloads the timer
11 Reserved (illegal setting)
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