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VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-25-
Register Summary Tables
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 1 Bus 0 Registers - PCI-to-AGP Bridge
PCI Configuration Registers
Offset Configuration Header
Default
Acc
1-0
Vendor ID
1106
RO
3-2
Device ID
8601
RO
5-4
Command
0007
RW
7-6
Status
0220
WC
8
Revision ID
nn
RO
9Program Interface
00
RO
A
Sub Class Code
04
RO
B
Base Class Code
06
RO
C
-reserved- (cache line size)
00
—
D
Latency Timer
00
RW
E
Header Type
01
RO
F
Built In Self Test (BIST)
00
RO
10-17 -reserved- (base address registers)
00
—
18
Primary Bus Number
00
RW
19
Secondary Bus Number
00
RW
1A
Subordinate Bus Number
00
RW
1B
-reserved- (secondary latency timer)
00
—
1C
I/O Base
F0
RW
1D
I/O Limit
00
RW
1F-1E Secondary Status
0000
RO
21-20 Memory Base
FFF0
RW
23-22 Memory Limit (Inclusive)
0000
RW
25-24 Prefetchable Memory Base
FFF0
RW
27-26 Prefetchable Memory Limit
0000
RW
28-3D -reserved- (unassigned)
00
—
3F-3E PCI-to-AGP Bridge Control
00
RW
Device-Specific Configuration Registers
Offset AGP Control
Default
Acc
40
CPU-to-AGP Flow Control 1
00
RW
41
CPU-to-AGP Flow Control 2
00
RW
42
AGP Master Control
00
RW
43-4F -reserved- (unassigned)
00
—