VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-87
VGA Extended Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
GR23 – Power Status ........................................................RW
7
Power Management Pin Polarity (see GR21[7])
6-5
Chip Power Status
00 Ready
01 Standby
10 Suspend
11 -reserved-
4
LCD Power Sequence Status
0
LCD power sequencing is not occurring at this
time
1
LCD power sequencing is occurring at this
time
3-2
Panel Power Sequencing
00 Fast panel power sequencing..................default
01 -reserved-
10 -reserved-
11 Slow panel power sequencing
1-0
DPMS Power Status
00 On Mode (CRT interface is active and
RAMDAC is full on) ..............................default
01 Standby Mode (Hsync disabled, Vsync active,
DAC off, RAMDAC color palette lookup
table (LUT) video data path is off but LUT
I/O is allowed)
10 Suspend Mode (Vsync disabled, Hsync active,
RAMDAC is off but contents are retained)
11 Off Mode (Hsync and Vsync disabled, DAC
LUT is full off)
In hardware mode, these bits indicate the status of
CRT Hsync and Vsync as well as the internal
RAMDAC power state (the “off” mode state can be
read only in CRT only mode). In software mode,
these bits control the state of the CRT Hsync and
Vsync signals but not the power state of the internal
RAMDAC.
In simultaneous display modes, the
power state of the RAMDAC is not controlled by the
DPMS Power State (bits 1-0), but by the Chip Power
State (bits 6-5).
GR24 – Software Power Control..................................... RW
7
VCLK
0
Disable
1Enable................................................... default
6MCLK
0
Disable
1Enable................................................... default
5
CPU & DRAM Data Bus
0
Disable
1Enable................................................... default
4
Reserved
........................................ always reads 0
3
ENPBLT
(Panel
and/or
Backlight
Enable)
Control
Software Power Control
0
Drive ENPBLT Low.............................. default
1
Drive ENPBLT High
Hardware Power Control (timers, pin, register bit)
0
ENPBLT is active low........................... default
1
ENPBLT is active high
2
Panel VDD
0
Disable................................................... default
1Enable
1
Panel Interface Signals
0
Disable................................................... default
1Enable
0Panel VEE
0
Disable................................................... default
1Enable
GR25 – Power Control Select .......................................... RW
When any of bits 7-6 or 3-0 are set to 1, the corresponding
power control bit reads back the logic state of the internal
power management engine.
For all bits below, 0 selects
hardware power control and 1 selects software power control.
7
Power Control for VCLK .............................. def = 1
6
Power Control for MCLK ............................ def = 1
5
Power Control for the Data Bus ................... def = 1
4
Power Control for the RAMDAC ................ def = 1
The RAMDAC is software enabled in GR26[7-6]
3
Power Control for Panel Enable / Backlight def = 1
(see GR24[3])
2
Power Control for Panel VDD ..................... def = 1
1
Power Control for Panel Interface Signals . def = 1
0
Power Control for Panel VEE ...................... def = 1
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
