Data Sheet

ADGS1408/ADGS1409

Rev. 0 | Page 31 of 34

ERROR CONFIGURATION REGISTER

Address: 0x02, Reset: 0x06, Name: ERR_CONFIG

The error configuration register allows the user to enable and disable the relevant error features as required.

Table 18. Bit Descriptions for ERR_CONFIG

Bit(s)

Bit Name

Settings

Description

Default

Access

[7:3]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

2

RW_ERR_EN

Enable bit for detecting an invalid read/write address.

0x1

R/W

0

Disabled.

1

Enabled.

1

SCLK_ERR_EN

Enable bit for detecting the correct number of SCLK cycles in an SPI frame.

16 SCLK cycles are expected when CRC is disabled and burst mode is disabled.

24 SCLK cycles are expected when CRC is enabled and burst mode is disabled.

A multiple of 16 SCLK cycles is expected when CRC is disabled and burst

mode is enabled. A multiple of 24 SCLK cycles is expected when CRC is

enabled and burst mode is enabled.

0x1

R/W

0

Disabled.

1

Enabled.

0

CRC_ERR_EN

Enable bit for CRC error detection. SPI frames are 24 bits wide when

enabled.

0x0

R/W

0

Disabled.

1

Enabled.

ERROR FLAGS REGISTER

Address: 0x03, Reset: 0x00, Name: ERR_FLAGS

The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI

command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user

must include the correct CRC byte during the SPI write for the clear error flags register command to succeed.

Table 19. Bit Descriptions for ERR_FLAGS

Bit(s)

Bit Name

Settings

Description

Default

Access

[7:3]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

2

RW_ERR_FLAG

Error flag for invalid read/write address. The error flag asserts during an

SPI read if the target address does not exist. The error flag also asserts

when the target address of an SPI write does not exist or is read only.

0x0

R

0

No error.

1

Error.

1

SCLK_ERR_FLAG

Error flag for the detection of the correct number of SCLK cycles in an SPI

frame.

0x0

R

0

No error.

1

Error.

0

CRC_ERR_FLAG

Error flag that determines if a CRC error occurred during a register write.

0x0

R

0

No error.

1

Error.