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CDCE706 Datasheet(PDF) 12 Page - Texas Instruments

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Part # CDCE706
Description  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
PDF  32 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CDCE706 Datasheet(HTML) 12 Page - Texas Instruments

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Default Device Setting
CDCE706
SCAS815A – OCTOBER 2005 – REVISED OCTOBER 2005
Table 2. Register Configuration Command Bitmap
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 0
Revision Code
Vendor Identification
Byte 1
PLL1 Reference Divider M 9-Bit [7:0]
Byte 2
PLL1 Feedback Divider N 12-Bit [7:0]
Byte 3
PLL1 Mux
PLL2 Mux
PLL3 Mux
PLL1 Feedback Divider N 12-Bit [11:8]
PLL1 Ref
Dev M [8]
Byte 4
PLL2 Reference Divider M 9-Bit [7:0]
Byte 5
PLL2 Feedback Divider N 12-Bit [7:0]
Byte 6
PLL1 fvco
PLL2 fvco
PLL3 fvco
PLL2 Feedback Divider N 12-Bit [11:8]
PLL2 Ref
Selection
Selection
Selection
Dev M [8]
Byte 7
PLL3 Reference Divider 9-Bit M [7:0]
Byte 8
PLL3 Feedback Divider N [12-Bit 7:0]
Byte 9
PLL Selection for P0 (Switch A)
PLL3 Feedback Divider N 12-Bit [11:8]
PLL3 Ref
Dev M [8]
Byte 10
PLL Selection for P1 (Switch A)
Inp. Clock
Configuration Inputs S1
Configuration Inputs S0
Selection
Byte 11
Input Signal Source
PLL Selection for P3 (Switch A)
PLL Selection for P2 (Switch A)
Byte 12
Reserved
Power Down
PLL Selection for P5 (Switch A)
PLL Selection for P4 (Switch A)
Byte 13
Reserved
7-Bit Divider P0 [6:0]
Byte 14
Reserved
7-Bit Divider P1 [6:0]
Byte 15
Reserved
7-Bit Divider P2 [6:0]
Byte 16
Reserved
7-Bit Divider P3 [6:0]
Byte 17
Reserved
7-Bit Divider P4 [6:0]
Byte 18
Reserved
7-Bit Divider P5 [6:0]
Byte 19
Reserved
Y0 Inv. or
Y0 Slew-Rate Control
Y0 Enable or
Y0 Divider Selection (Switch B)
Non-Inv
Low
Byte 20
Reserved
Y1 Inv. or
Y1 Slew-Rate Control
Y1 Enable or
Y1 Divider Selection (Switch B)
Non-Inv
Low
Byte 21
Reserved
Y2 Inv. or
Y2 Slew-Rate Control
Y2 Enable or
Y2 Divider Selection (Switch B)
Non-Inv
Low
Byte 22
Reserved
Y3 Inv. or
Y3 Slew-Rate Control
Y3 Enable or
Y3 Divider Selection (Switch B)
Non-Inv
Low
Byte 23
Reserved
Y4 Inv. or
Y4 Slew-Rate Control
Y4 Enable or
Y4 Divider Selection (Switch B)
Non-Inv
Low
Byte 24
EEPIP [read
Y5 Inv or
Y5 Slew-Rate Control
Y5 Enable or
Y5 Divider Selection (Switch B)
only]
Non-Inv
Low
Byte 25
EELOCK
Spread Spectrum (SSC) Modulation
Frequency Selection for SSC
Selection
Byte 26
EEWRITE
7-Bit Byte Count
The internal EEPROM of CDCE706 is pre-programmed with a factory default configuration as shown below. This
puts the device in an operating mode without the need to program it first. The default setting appears after power
is switched on or after a power-down/up sequence until it is re-programmed by the user to a different application
configuration. A new register setting is programmed via the serial SMBUS Interface.
A different default setting can be programmed upon customer request. Contact a Texas Instruments sales or
marketing representative for more information.
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