LM5145 datasheet(5/62 Pages) TI

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Table 6-1. Pin Functions (continued)

I/O(1)

DESCRIPTION

NO.

NAME

SYNCOUT

Synchronization output. Logic output that provides a clock signal that is 180° out-of-phase with the high-side

FET gate drive. Connect SYNCOUT of the master LM5145-Q1 to the SYNCIN pin of a second LM5145-Q1 to

operate two controllers at the same frequency with 180° interleaved high-side FET switch turn-on transitions.

Note that the SYNCOUT pin does not provide 180° interleaving when the controller is operating from an

external clock that is different from the free-running frequency set by the RT resistor.

SYNCIN

Dual function pin to provide an optional clock input and enable diode emulation by the low-side MOSFET.

Connecting a clock signal to the SYNCIN pin synchronizes switching to the external clock. Diode emulation

by the low-side MOSFET is disabled when the controller is synchronized to an external clock, and negative

inductor current can flow in the low-side MOSFET with light loads. A continuous logic low state at the

SYNCIN pin enables diode emulation to prevent reverse current flow in the inductor. Diode emulation results in

discontinuous mode operation (DCM) at light loads, which improves efficiency. A logic high state at the SYNCIN

pin disables diode emulation, producing forced-PWM (FPWM) operation. During soft start when SYNCIN is high

or a clock signal is present, the LM5145-Q1 operates in diode emulation mode until the output is in regulation,

then gradually increases the SW zero-cross threshold, resulting in a gradual transition from DCM to FPWM.

—

No electrical connection

PGOOD

Power-good indicator. This pin is an open-drain output. A high state indicates that the voltage at the FB pin is

within a specified tolerance window centered at 0.8 V.

ILIM

Current limit adjust and current sense comparator input. A current sourced from the ILIM pin through an

external resistor programs the threshold voltage for valley current limiting. The opposite end of the threshold

adjust resistor can be connected to either the drain of the low-side MOSFET for RDS(on) sensing or to a current

sense resistor connected to the source of the low-side FET.

PGND

Power ground return pin for the low-side MOSFET gate driver. Connect directly to the source of the low-side

MOSFET or the ground side of a shunt resistor.

Low-side MOSFET gate drive output. Connect to the gate of the low-side synchronous rectifier FET through a

short, low inductance path.

VCC

Output of the 7.5-V bias regulator. Locally decouple to PGND using a low-ESR/ESL capacitor located as close

as possible to the controller. Controller bias can be supplied from an external supply that is greater than the

internal VCC regulation voltage. Use caution when applying external bias to ensure that the applied voltage is

not greater than the minimum VIN voltage and does not exceed the VCC pin maximum operating rating. See the

Recommended Operating Conditions.

—

Pin is internally connected to exposed pad of the package. Connect to GND at the exposed pad to improve

heat spreading.

—

No electrical connection

BST

Bootstrap supply for the high-side gate driver. Connect to the bootstrap (boot) capacitor. The bootstrap

capacitor supplies current to the high-side FET gate and must be placed as close as possible to controller.

If an external bootstrap diode is used to reduce the time required to charge the bootstrap capacitor, connect the

cathode of the diode to the BST pin and anode to VCC.

High-side MOSFET gate drive output. Connect to the gate of the high-side MOSFET through a short, low

inductance path.

Switching node of the buck controller. Connect to the bootstrap capacitor, the source terminal of the high-side

MOSFET, and the drain terminal of the low-side MOSFET using short, low inductance paths.

VIN

Supply voltage input for the VCC LDO regulator

—

Exposed pad of the package. Electrically isolated. Solder to the system ground plane to reduce thermal

resistance.

(1)

P = Power, G = Ground, I = Input, O = Output

6.1 Wettable Flanks

100% automated visual inspection (AVI) post-assembly is typically required to meet requirements for high

reliability and robustness. Standard quad-flat no-lead (VQFN) packages do not have solderable or exposed pins

and terminals that are easily viewed. Therefore, it is difficult to visually determine whether or not the package

is successfully soldered onto the printed-circuit board (PCB). The wettable-flank process was developed to

resolve the issue of side-lead wetting of leadless packaging. The LM5145-Q1 is assembled using a 20-pin VQFN

package with wettable flanks to provide a visual indicator of solderability, which reduces the inspection time and

manufacturing costs.

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LM5145-Q1

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