LM5145 datasheet(30/62 Pages) TI

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with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such

losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching

period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases

where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect

two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses

due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode

reverse recovery. The LM5145-Q1 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.

9.1.3 Control Loop Compensation

The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue

dashed rings in the schematic embedded in Table 9-2. The compensation network typically employed with

voltage-mode control is a Type-III circuit with three poles and two zeros. One compensator pole is located at

the origin to realize high DC gain. The normal compensation strategy uses two compensator zeros to counteract

the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining

compensator pole located at one-half switching frequency to attenuate high frequency noise. The resistor divider

network to FB determines the desired output voltage. Note that the lower feedback resistor, RFB2, has no

impact on the control loop from an AC standpoint because the FB node is the input to an error amplifier and is

effectively at AC ground. Hence, the control loop is designed irrespective of output voltage level. The proviso

here is the necessary output capacitance derating with bias voltage and temperature.

Table 9-2. Buck Regulator Poles and Zeros

COMP

VIN

VOUT

GND

Adaptive

Gate

Driver

RFB2

RC2

CC3

CC2

RFB1

RC1

CC1

VREF

PWM

Comparator

PWM Ramp

&p1

&z1

RESR

&p2

&z2

&ESR

Modulator

Compensator

Power Stage

IOUT

VRAMP

Error

Amp

RDAMP

COUT

POWER STAGE POLES

POWER STAGE ZEROS

COMPENSATOR POLES

COMPENSATOR ZEROS

ESR

OUT

ESR

DAMP

OUT

(1) (2)

ESR

OUT

)

DAMP

FB1

) C

(1)

RESR represents the ESR of the output capacitor COUT.

(2)

RDAMP = D · RDS(on)high-side + (1–D) · RDS(on) low-side + RDCR, shown as a lumped element in the schematic, represents the effective

series damping resistance.

The small-signal open-loop response of a buck regulator is the product of modulator, power train and

compensator transfer functions. The power stage transfer function can be represented as a complex pole pair

LM5145-Q1

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