ACE25AA320GFMLTH datasheet(32/67 Pages) ACE

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ACE25AA320G

Serial NOR Flash Memory

3.0V Multi I/O with 4KB, 32KB & 64KB Sector/Block Erase

VER 1.2

The Sector Erase command sequence: CS# goes low→sending Sector Erase command→3-byte address

on SI→CS# goes high. The command sequence is shown in Figure16. CS# must be driven high after the

eighth bit of the last address byte has been latched in; otherwise the Sector Erase (SE) command is not

executed. As soon as CS# is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value

of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase

cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write

Enable Latch (WEL) bit is reset. A Sector Erase( (SE) command applied to a sector which is protected by

the Block Protect(BP4, BP3,BP2, BP1, and BP0) bit (see Table1 &1.1) will not be executed.

32KB Block Erase (BE) (52H)

The 32KB Block Erase (BE) command is for erasing the all data of the chosen block. A Write Enable

(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The

32KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and

three address bytes on SI. Any address inside the block is a valid address for the 32KB Block Erase (BE)

command. CS# must be driven low for the entire duration of the sequence.

Figure16. Sector Erase Sequence Diagram

Figure16a. Sector Erase Sequence Diagram (QPI)

ACE25AA320GFMLTH Datasheet(PDF) 32 Page - ACE Technology Co., LTD.