ACE25AB400G

Serial NOR Flash Memory 4M bits 3.0V Dual I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

24

Erase Security Registers (44H)

The ACE25AB400G provides two 256-byte Security Registers which only erased all at once but able to

pro- gram individually. These registers may be used by the system manufacturers to store security and

other important information separately from the main memory array.

The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable

(WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit.

The Erase Security Registers command sequence: CS# goes low, sending Erase Security Registers

Command, CS# goes high. CS# must be driven high after the eighth bit of the command code has been

latched in, otherwise the Erase Security Registers command is not executed. As soon as CS# is driven

high, the self-timed Erase Security Registers cycle (whose duration is tSE) is initiated.

While the Erase Security Registers cycle is in progress, the Status Register may be read to check the

value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Erase

Security Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset. The Security Registers Lock Bit (LB) in the Status

Register can be used to OTP protect the security registers. Once the LB bit is set to 1, the Security

Registers will be permanently locked; the Erase Security Registers command will be ignored.

Address

A23-A16

A15-A10

A9-A0

Security Registers

00000000

000000

Don’t Care

Figure22. Erase Security Registers command Sequence Diagram