ACE25AB400GFMLTH datasheet(4/37 Pages) ACE

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ACE25AB400G

Serial NOR Flash Memory 4M bits 3.0V Dual I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

Device Operation

Standard SPI

The ACE25AB400G features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip

Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are

supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of

SCLK.

Dual SPI

The ACE25AB400G supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O

Fast Read” (3BH and BBH) commands. These commands allow data to be transferred to or from the

device at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins

become bidirectional I/O pins: IO0 and IO1.

Data Protection

The ACE25AB400G provides the following data protection methods:

Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL

bit will return to reset by the following situation:



Power-Up



Write Disable (WRDI)



Write Status Register (WRSR)



Page Program (PP)



Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)

Software Protection Mode:



SRWD=0, the Block Protect (BP1, BP0) bits define the section of the memory array that can be read

but not change



SRWD=1, the Write Status Register (WRSR) instruction is no longer accepted for execution and the

SRWD bit and Block Protect bits (BP1, BP0) are read only.

Table 1.ACE25AB400G Protected Area Sizes

Status bit

Protect level

Protect Block

BP1

BP2

BP0

0(none)

None

1 (1 block)

Block 7

2 (2 blocks)

Block 6-7

3 (4 blocks)

Block 4-7

4 (8 blocks)

All

5 (All)

All

6 (All)

All

7 (All)

All

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