ACE25AB400G

Serial NOR Flash Memory 4M bits 3.0V Dual I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

5

Status Register

S7

S6

S5

S4

S3

S2

S1

S0

SRWD

LB1

LB0

BP2

BP1

BP0

WEL

WIP

The status and control bits of the Status Register are as follows:

WIP bit.

The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status

regis- ter progress. When WIP bit sets to 1, means the device is busy in program/erase/write status

register progress, when WIP bit sets 0, means the device is not in program/erase/write status register

progress.

WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1

the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write

Status Register, Program or Erase command is accepted.

LB1, LB0 bits.

The LB1, LB0 are non-volatile One Time Program (OTP) bits in Status Register (S5) that provide the write

protect control and status to the Security Registers. The default state of LB1 and LB0 are 0, the security

registers are unlocked. LB1, LB0 can be set to 1 using the Write Register instruction. LB1, LB0 are One

Time Programmable, once they were set to 1, the corresponding Security Registers will become

read-only permanently.

BP2, BP1, BP0 bits.

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase commands. These bits are written with the Write Status Register

(WRSR) command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area

(as defined in Table1.0) becomes protected against Page Program (PP), Sector Erase (SE) and Block

Erase (BE) commands. Chip Erase command will be ignored if one or more of the Block Protect (BP2,

BP1, BP0) bits are 1.

SRWD bit.

The Status Register Write Disable (SRWD) bit is a non-volatile One Time Program(OTP) bit in the status

reg- ister that provide another software protection. Once it is set to 1, the Write Status Register (WRSR)

instruction is not accepted and the Block Protect bits (BP2, BP1, BP0) are read only.

SRWD

Status register

0

Status register can be written in (WEL bit is set to “1”) and the SRWD, BP2-BP0 bits can be

changed

1

The BP2-BP0 of status register bits cannot be changed