MPC755EC datasheet(32/56 Pages) NXP

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

Package Description

The following sections provide the package parameters and mechanical dimensions for the MPC745, 255

PBGA package, as well as the MPC755, 360 CBGA and PBGA packages. While both the MPC755 plastic

and ceramic packages are described here, both packages are not guaranteed to be available at the same

time. All new designs should allow for either ceramic or plastic BGA packages for this device. For more

information on designing a common footprint for both plastic and ceramic package types, see the

Freescale Flip-Chip Plastic Ball Grid Array Presentation. The MPC755 was initially sampled in a CBGA

package, but production units are currently provided in both a CBGA and a PBGA package. Because of

the better long-term device-to-board interconnect reliability of the PBGA package, Freescale recommends

use of a PBGA package except where circumstances dictate use of a CBGA package.

VOLTDET

K13

High

Output

L2OVDD

Notes:

1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and

L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:16], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT) and

the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become AVDD

and L2AVDD, respectively). These columns serve as a reference for the nominal voltage supported on a given signal as

selected by the BVSEL/L2VSEL pin configurations of Table 2 and the voltage supplied. For actual recommended value of Vin

or supply voltages, see Table 3.

2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.

3. This pin must be pulled up to OVDD for proper operation of the processor interface. To allow for future I/O voltage changes,

provide the option to connect BVSEL independently to either OVDD or GND.

4. These pins are reserved for potential future use as additional L2 address pins.

5. Uses one of nine existing no connects in the MPC750, 360 BGA package.

6. Internal pull-up on die.

7. This pin must be pulled up to L2OVDD for proper operation of the processor interface. To allow for future I/O voltage changes,

provide the option to connect L2VSEL independently to either L2OVDD or GND.

8. Internally tied to L2OVDD in the MPC755, 360 BGA package to indicate the power present at the L2 cache interface. This

signal is not a power supply input.

Caution: This differs from the MPC745, 255 BGA package.

Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued)

Signal Name

Pin Number

Active

I/O

I/F Voltage 1

Notes

MPC755EC Datasheet(PDF) 32 Page - NXP Semiconductors

MPC755EC Datasheet(HTML) 32 Page - NXP Semiconductors

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