11

AT25DN011

DS-25DN011–038H–8/2021

that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page.

For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then

the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be

programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be

programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device,

then only the last 256 bytes sent will be latched into the internal buffer.

When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the

appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes

sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not

be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and

The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is

deasserted, and the CS pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will

abort the operation and no data will be programmed into the memory array. In addition, if the memory is in the protected

state (see “Block Protection” on page 15), then the Byte/Page Program command will not be executed, and the device

will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to

the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data

being sent, the CS pin not being deasserted on byte boundaries, or because the memory location to be programmed is

protected.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster

data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status

Register will be reset back to the logical “0” state.

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program

properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

Figure 8-1. Byte Program

SCK

CS

SI

SO

MSB

MSB

23

1

0

00000010

67

5

410 11

9

812

39

37 38

33

36

35

34

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AAAA

AAA

A

A

MSB

DDDDDDD

D

ADDRESS BITS A23-A0

DATA IN