12

AT25DN011

DS-25DN011–038H–8/2021

Figure 8-2. Page Program

8.2

Page Erase

Page Erase for 1Mbit, 512 Pages [nine (9) page address bits, PA<8:0>] of 256Bytes each.

The Page Erase command can be used to individually erase any page in the main memory array. The Main Memory

Byte/Page Program command can be utilized at a later time.

To perform a Page Erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the device

followed by three address bytes comprised of:

Byte 0: 81h the page erase command code

Byte 1: XXXX XXX, PA8; which is seven (7) dummy bits, and one (1) page address bit PA8

Byte 2: PA<7:0>; which is eight (8) page address bits

Byte 3: XXXX XXXX; which is eight (8) dummy bits

When a low-to-high transition occurs on the CS pin, the device will erase the selected page (the erased state is a Logic

RDY/BUSY bit in the Status Register will indicate that the device is busy.

The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If

an erase error arises, it will be indicated by the EPE bit in the Status Register.

8.3

Block Erase

A block of 4 or 32 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three

different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, and an opcode of 52h or

D8h is used for a 32-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have

been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be

clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the

4- or 32-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When

the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the

device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a

logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. Despite the lower order

address bits not being decoded by the device, the complete three address bytes must still be clocked into the device

before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);

otherwise, the device will abort the operation and no erase operation will be performed.

If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to

the idle state once the CS pin has been deasserted.

SCK

CS

SI

SO

MSB

MSB

23

1

0

00000010

67

5

49

839

37 38

33

36

35

34

31 32

29 30

OPCODE

HIGH-IMPEDANCE

AA

AAA

A

MSB

DDDDDDD

D

ADDRESS BITS A23-A0

DATA IN BYTE 1

MSB

DDDDDDD

D

DATA IN BYTE n