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ADA4558WHCPZ-R7 Datasheet(PDF) 3 Page - Analog Devices |
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ADA4558WHCPZ-R7 Datasheet(HTML) 3 Page - Analog Devices |
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3 / 12 page ![]() Data Sheet ADA4558 Rev. 0 | Page 3 of 12 SPECIFICATIONS Supply voltage (VDD12) = 12 V, common-mode voltage (VCM) = 2 V, and TA = 25°C, unless otherwise specified. Minimum and maximum values are specified over the full supply voltage and a temperature range of −40°C to +150°C. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit POWER SUPPLY (SYSTEM) Supply Voltage VDD12 6 12 18 V Operating Range1 VDD12, LOAD DUMP Load dump for 0.3 sec 27 V VDD12, JUMP START Jump start for 60 sec 26 V Undervoltage Lockout (UVLO) VUVLO Rising 5.1 V Hysteresis 0.2 V Supply Current ISY Normal operation, VREG current (IVREG), LIN current (ILIN) = 0 mA, TA = −40°C to +85°C 5.0 7 mA Normal operation, IVREG, ILIN = 0 mA, TA = −40°C to +150°C 8.2 mA Sleep Mode Current Enabled with inactivity on the LIN bus 150 µA VREG Output VREG 3.8 4.0 4.2 V VREG Temperature Coefficient2 95 ppm/°C DVDD Regulated Voltage DVDD 1.6 1.8 2.0 V SYSTEM SPECIFICATIONS Full-Scale Accuracy with Calibration Sensor characteristic dependent PGA gain = 2.94 V/V to 162.52 V/V 0.1 % FSR PGA gain = 224.72 V/V to 971.10 V/V 0.25 % FSR INPUT STAGE PGA Gain Setting 2.94 971.10 V/V Common-Mode Input Voltage Range 34 65 % VREG Bridge Resistance RBR 2 20 kΩ Input Electromagnetic Interference (EMI) Filter3 Cutoff Frequency (f−3 dB) Differential 0.55 MHz f−3dB Common Mode 0.58 MHz Input Offset Voltage4 VOS 5 20 µV Voltage Drift TCVOS 10 nV/°C Maximum Input Capacitance VPOS/VNEG nodes 15 nF COARSE OFFSET5 Bridge Offset Cancellation Range At PGA input ±60 mV/V Offset Trim Resolution PGA gain = 2.94 6 Bits PGA gain = 971.10 14 Bits Step Size At PGA output 31 mV COARSE GAIN Gain Setting Accuracy Gain = 2.94 to 162.52 −1.2 ±0.2 +1.2 % Gain = 224.72 to 971.10 −2.75 ±1 +2.75 % Gain Error Temperature Coefficient Gain ≤ 573.0 50 ppm/°C Gain = 722.3 64 ppm/°C Gain = 971.10 121 ppm/°C ADC PERFORMANCE Main ADC Resolution 14 Bits ADC Integral Nonlinearity (INL) −4 +4 LSB14 ADC Differential Nonlinearity (DNL) −1 +1 LSB14 |
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