Data Sheet

ADA4558

Rev. 0 | Page 5 of 12

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Start-Up Time (System)

First readback of valid data, filter

setting = 500 Hz, all faults enabled or

disabled

100

ms

Main Oscillator Frequency

All internal timers are related to

oscillator

9.5

10

10.5

MHz

Oscillator Frequency (Sleep Mode)

300

kHz

ELECTRICALLY ERASABLE

PROGRAMMABLE READ-ONLY

MEMORY (EEPROM)

Programming

Number of Cycles

1000

Cycles

Time

Per 32-bit written word

20

40

ms

Temperature

−40

+150

°C

Data Retention

1000 write cycles, operation at 150°C

10

Years

1000 write cycles, 40,000 hour

operation (10,000 hours at 55°C +

27,000 hours at 125°C + 3000 hours at

150°C)

15

Years

FAULTS

Bridge Sensor Input Bias Current

Detects input open circuit (startup)

5

µA

Detects input open circuit,

normal/running mode operation

(EEPROM register

PGA_ADD_PULUP_150 = 0), default

300

nA

Detects input open circuit,

normal/running mode operation

(EEPROM register

PGA_ADD_PULUP_150 = 1)

450

nA

Input Open Detection Resistance

Startup

320

kΩ

Normal running mode operation

32

MΩ

Open Detection Threshold

Low

18.75

High

81.25

Input Short Detection Resistance

0.5

kΩ

Oscillator Crosscheck Limit

14

%

External Temperature Sensor Bias

Current

Detects external temperature open

circuit

28

nA

Thermal Shutdown

170

°C

Hysteresis

7

°C

1

Guaranteed by absolute maximum ratings (see the Absolute Maximum Ratings section).

2

The VREG voltage is also the reference to the ADC. Therefore, reference temperature drift does not affect system error. This specification can be useful in gain and

offset selection at EOL calibration.

3

Guaranteed by design.

4

Errors in PGA, temperature sensor gain, offset, and temperature drift are eliminated based on the EOL calibration routine.

5

The input offset trim range is −60 mV/V to +60 mV/V. The ADC reference is 4 V. The resulting input offset trim range is 0.48 V. The output preferred offset trim

resolution is 31 mV. For a gain of 2.9, the input referred offset trim resolution is 10.6 mV. Dividing range by resolution gives approximately 50 steps, which is close to a

6-bit resolution. For a gain of 971, the input referred offset trim resolution is 32 μV. Dividing range by resolution equals 16,287 LSBs, which is close to 14-bit resolution.

In all cases, this only provides the coarse offset calibration required to get the PGA output into the valid ADC range of operation. The digital linearization engine

provides fine offset calibration to meet the system accuracy targets.