ADUC7121BBCZ datasheet(26/102 Pages) AD

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ADuC7120/ADuC7121

Data Sheet

Rev. D | Page 26 of 102

ARM REGISTERS

ARM7TDMI has a total of 37 registers: 31 general-purpose

registers and 6 status registers. Each operating mode has

dedicated banked registers.

When writing user level programs, 15 general-purpose 32-bit

registers (R0 to R14), the program counter (R15), and the current

program status register (CPSR) are usable. The remaining

registers are used for system level programming and exception

handling only.

When an exception occurs, some of the standard registers are

replaced with registers specific to the exception mode. All

exception modes have replacement banked registers for the

stack pointer (R13) and the link register (R14) as represented

in Figure 9. The fast interrupt mode has more registers (R8 to

R12) for fast interrupt processing, which means that interrupt

processing can begin without the need to save or restore these

registers, thus saving critical time in the interrupt handling

process.

USABLE IN USER MODE

SYSTEM MODES ONLY

SPSR_UND

SPSR_IRQ

SPSR_ABT

SPSR_SVC

R8_FIQ

R9_FIQ

R10_FIQ

R11_FIQ

R12_FIQ

R13_FIQ

R14_FIQ

R13_UND

R14_UND

R10

R11

R12

R13

R14

R15 (PC)

R13_IRQ

R14_IRQ

R13_ABT

R14_ABT

R13_SVC

R14_SVC

SPSR_FIQ

CPSR

USER MODE

FIQ

MODE

SVC

MODE

ABORT

MODE

IRQ

MODE

UNDEFINED

MODE

Figure 9. Register Organization

More information relative to the model of the programmer and

the ARM7TDMI core architecture can be found in the following

materials from ARM, Ltd.:

•

ARM DDI 0029G, ARM7TDMI Technical Reference Manual

•

ARM DDI 0100, ARM Architecture Reference Manual

INTERRUPT LATENCY

The worst case latency for a FIQ consists of the following:

•

The longest time the request can take to pass through the

synchronizer.

•

The time for the longest instruction to complete (the

longest instruction is a load multiple (LDM)) that loads all

the registers including the PC.

•

The time for the data abort entry.

•

The time for FIQ entry.

At the end of this time, the ARM7TDMI executes the instruction at

0x1C (FIQ interrupt vector address). The maximum total time

is 50 processor cycles, which is just under 1.2 µs in a system

using a continuous 41.78 MHz processor clock.

The maximum IRQ latency calculation is similar but must allow

the fact that FIQ has higher priority and can delay entry into

the IRQ handling routine for an arbitrary length of time. This

time can be reduced to 42 cycles if the LDM command is not

used. Some compilers have an option to compile without using this

command. Another option is to run the devices in thumb mode

wherein the time is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is five cycles,

which consist of the shortest time the request can take through

the synchronizer plus the time to enter the exception mode.

The ARM7TDMI always runs in ARM (32-bit) mode when in

privileged modes, for example, when executing interrupt

service routines.

ADUC7121BBCZ Datasheet(PDF) 26 Page - Analog Devices

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