ADUC7121BBCZ datasheet(52/102 Pages) AD

52 / 102 page

ADuC7120/ADuC7121

Data Sheet

Rev. D | Page 52 of 102

Table 67. IDAC Bandwidth Registers (Default Value = 0x00,

Read and Write Access)

Name

Address

IDAC0BW

0xFFFF0708

IDAC1BW

0xFFFF0714

IDAC2BW

0xFFFF0720

IDAC3BW

0xFFFF072C

IDAC4BW

0xFFFF0738

Table 68. IDACxBW MMR Bit Designations

Bit(s)

Name

Setting

Description

[7:4]

Reserved

The user sets these bits to 0.

[3:0]

Bandwidth control bits. Defines

the 3 dB bandwidth of the

resistor capacitor (RC) low-pass

filter, assuming a 0.01 μF

capacitor on the CDAMP_IDACx

pins of the IDACx.

000

100 kHz.

001

28.7 kHz.

010

15 kHz.

011

7.8 kHz.

100

4 kHz.

101

2.2 kHz.

110

1.2 kHz.

Others

Not defined.

Table 69. IDAC Status Register (Default Value = 0x00, Read

and Write Access)

Name

Address (Hex)

IDACSTA

0xFFFF0740

Table 70. IDACSTA MMR Bit Designations

Bit(s)

Name

Setting

Description

[7:2]

Reserved

These bits are set to 0 by the user.

TSHUT

Thermal shutdown error status

bit.

Set to 1 by the core indicating a

thermal shutdown event.

Set to 0 by the core indicating

the IDACs are within operating

temperature.

Reserved

Reserved.

OSCILLATOR AND PLL—POWER CONTROL

The ADuC7120/ADuC7121 integrate a 32.768 kHz oscillator, a

clock divider, and a phase-locked loop (PLL). The PLL locks

onto a multiple (1275) of the internal oscillator to provide a

stable 41.78 MHz clock for the system. The core can operate at

this frequency, or at binary submultiples of it, to allow power

saving. The default core clock is the PLL clock divided by 8

(CD = 3) or 5.2 MHz. The core clock frequency can be output on

the XCLK pin as described in Figure 34. When the XCLK pin

outputs the core clock, the output signal is not buffered and is

not suitable for use as a clock source to an external device

without an external buffer.

A power-down mode is available on the ADuC7120/ADuC7121.

The operating mode, clocking mode, and programmable clock

divider are controlled via two MMRs: PLLCON (see Table 73) and

POWCON (see Table 74). PLLCON controls the operating

mode of the clock system, and POWCON controls the core

clock frequency and the power-down mode.

AT POWER-UP

41.78MHz

OCLK 32.768kHz

WATCHDOG

TIMER

INT. 32kHz1

OSCILLATOR

CRYSTAL

OSCILLATOR

TIMERS

MDCLK

HCLK

PLL

CORE

I2C

UCLK

ANALOG

PERIPHERALS

/2CD

XTALO

XTALI

P1.4/XCLK

P1.4/ECLK

132.768kHz ±3%

Figure 34. Clocking System

External Crystal Selection

To switch to an external crystal, use the following procedure:

1. Enable the Timer2 interrupt and configure it for a timeout

period of >120 µs.

2. Follow the write sequence to the PLLCON register, setting

the MDCLK bits to 01 and clearing the OSEL bit.

3. Force the device into nap mode by writing the correct write

sequence to the POWCON register.

4. When the device is interrupted from nap mode by the Timer2

interrupt source, the clock source switches to the external

clock.

In noisy environments, noise can couple to the external crystal

pins, and PLL can lose lock momentarily. A PLL interrupt is

provided in the interrupt controller. The core clock is immediately

halted, and this interrupt is serviced only when the lock is restored.

ADUC7121BBCZ Datasheet(PDF) 52 Page - Analog Devices

ADUC7121BBCZ Datasheet(HTML) 52 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL