ADUC7121BBCZ datasheet(25/102 Pages) AD

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Data Sheet

ADuC7120/ADuC7121

Rev. D | Page 25 of 102

OVERVIEW OF THE ARM7TDMI CORE

The ARM7™ core is a 32-bit reduced instruction set computer

(RISC). It uses a single 32-bit bus for instruction and data. The

length of the data can be 8 bits, 16 bits, or 32 bits. The length of

the instruction word is 32 bits.

The ARM7TDMI® is an ARM7 core with four additional

features, as follows:

•

T support for the thumb (16-bit) instruction set

•

D support for debug

•

M support for long multiplications

•

I includes the EmbeddedICE™ module to support

embedded system debugging

THUMB (T) MODE

An ARM® instruction is 32 bits long. The ARM7TDMI processor

supports a second instruction set that has been compressed into

16 bits, the Thumb® instruction set. Faster execution from 16-bit

memory and greater code density can usually be achieved by

using the Thumb instruction set instead of the ARM instruction

set, which makes the ARM7TDMI core suitable for embedded

applications.

However, the Thumb mode has the following two limitations:

•

Thumb code typically requires more instructions for the

same job. As a result, ARM code is usually best for

maximizing the performance of time critical code.

•

The Thumb instruction set does not include some of the

instructions needed for exception handling, which

automatically switches the core to ARM code for exception

handling.

See the ADuC7XXX Microconverter™ Get Started Guide for

details on the core architecture, the programming model, and

both the ARM and ARM Thumb instruction sets.

LONG MULTIPLY (M)

The ARM7TDMI instruction set includes four extra

instructions that perform 32-bit by 32-bit multiplication with a

64-bit result, and 32-bit by 32-bit multiplication accumulation

(MAC) with a 64-bit result. These results are achieved in fewer

cycles than required on a standard ARM7 core.

EmbeddedICE (I)

EmbeddedICE provides integrated on-chip support for the core.

The EmbeddedICE module contains the breakpoint and watch-

point registers that halts code for debugging purposes. These

registers are controlled through the JTAG test port.

When a breakpoint or watchpoint is encountered, the processor

halts and enters a debug state. When in a debug state, the

breakpoint and watchpoint registers can be inspected, as well

as the Flash/EE, static random access memory (SRAM), and

memory mapped registers.

EXCEPTIONS

ARM supports five types of exceptions and a privileged

processing mode for each type. The five exception types include

the following:

•

Normal interrupt (IRQ) can service general-purpose

interrupt handling of internal and external events.

•

Fast interrupt (FIQ) can service data transfers or

communication channels with low latency.; FIQ has

priority over IRQ.

•

Memory abort.

•

Attempted execution of an undefined instruction.

•

Software interrupt instruction (SWI) can make a call to an

operating system.

Typically, the programmer defines interrupt as IRQ, but for

higher priority interrupt, that is, faster response time, the

programmer can define interrupt as FIQ.

ADUC7121BBCZ Datasheet(PDF) 25 Page - Analog Devices

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