ADUC7121BBCZ datasheet(80/102 Pages) AD

80 / 102 page

ADuC7120/ADuC7121

Data Sheet

Rev. D | Page 80 of 102

PLACLK Register

PLACLK is the clock selection for the flip-flops of Block 0 and

Block 1. The maximum frequency when using the GPIO pins as

the clock input for the PLA blocks is 41.78 MHz.

Name:

PLACLK

Address:

0xFFFF0B40

Default value: 0x00

Access:

Read and write

Table 111. PLACLK MMR Bit Descriptions

Bit(s)

Setting

Description

Reserved.

[6:4]

Block 1 clock source selection.

000

GPIO clock on P0.5 of the P0.5/CS/PLAI[10]/

ADCCONVST pin.

001

GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin.

010

GPIO clock on the P0.7 of the P0.7/TRST/PLAI[3]

pin.

011

HCLK (core clock).

100

OCLK (32.768 kHz external crystal).

101

Timer1 overflow.

Other

Reserved.

[2:0]

Block 0 clock source selection.

000

GPIO clock on P0.5. on P0.5 of the P0.5/CS/

PLAI[10]/ADCCONVST pin.

001

GPIO clock on P0.0 of the P0.0/SCL0/PLAI[5] pin.

010

GPIO clock on P0.7 of the P0.7/TRST/PLAI[3] pin.

011

HCLK (core clock).

100

OCLK (32.768 kHz external crystal).

101

Timer1 overflow.

Other

Reserved.

PLAIRQ Register

PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of

the normal interrupt request IRQ (IRQ).

Name:

PLAIRQ

Address:

0xFFFF0B44

Default value: 0x0000

Access:

Read and write

Table 112. PLAIRQ MMR Bit Descriptions

Bit(s)

Setting

Description

[15:13]

Reserved.

PLA IRQ1 enable bit.

Set by the user to enable IRQ1 output from

the PLA.

Cleared by the user to disable IRQ1 output

from the PLA.

Bit(s)

Setting

Description

[11:8]

PLA IRQ1 source.

0000

PLA Element 0.

0001

PLA Element 1.

1111

PLA Element 15.

[7:5]

Reserved.

PLA IRQ0 enable bit.

Set by the user to enable IRQ0 output from

the PLA.

Cleared by the user to disable IRQ0 output

from the PLA.

[3:0]

PLA IRQ0 source.

0000

PLA Element 0.

0001

PLA Element 1.

1111

PLA Element 15.

PLAADC Register

PLAADC is the PLA source for the ADC start conversion signal.

Name:

PLAADC

Address:

0xFFFF0B48

Default value: 0x00000000

Access:

Read and write

Table 113. PLAADC MMR Bit Descriptions

Bit(s)

Setting

Description

[31:5]

Reserved.

ADC start conversion enable bit.

Set by the user to enable an ADC start

conversion from the PLA.

Cleared by the user to disable an ADC start

conversion from the PLA.

[3:0]

ADC start conversion source.

0000

PLA Element 0.

0001

PLA Element 1.

1111

PLA Element 15.

PLADIN Register

PLADIN is a data input MMR for PLA.

Name:

PLADIN

Address:

0xFFFF0B4C

Default value: 0x00000000

Access:

Read and write

Table 114. PLADIN MMR Bit Descriptions

Bit(s)

Description

[31:16]

Reserved.

[15:0]

Input bit from Element 15 to Element 0.

ADUC7121BBCZ Datasheet(PDF) 80 Page - Analog Devices

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