ADUC7121BBCZ datasheet(51/102 Pages) AD

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Data Sheet

ADuC7120/ADuC7121

Rev. D | Page 51 of 102

IDAC MMRS

Table 61. IDAC Control Registers (Read and Write Access)

Name

Address (Hex)

Default Value

IDAC0CON

0xFFFF0700

0x0010

IDAC1CON

0xFFFF070C

0x0010

IDAC2CON

0xFFFF0718

0x0010

IDAC3CON

0xFFFF0724

0x0010

IDAC4CON

0xFFFF0730

0x0010

TDSCON

0xFFFF073C

0x00

IDAC0PULLDOWN

0xFFFF0744

0x00

Table 62. IDACxCON MMR Bit Designations

Bit(s)

Name

Setting

Description

[15:9]

These bits are reserved.

[8:7]

SFHMODE

Bit shuffling is a method of

increasing the ac precision of

an IDAC. Do not use in

applications where dc

performance is important.

Shuffle one increment at a

time.

Shuffle based on an internal

counter.

Shuffle based on the input

data.

Reserved.

MSBSHFEN

MSB shuffle enable.

Set by the user to 1 to enable

MSB shuffling.

Set by the user to 0 to disable

MSB shuffling.

LSBSHFEN

LSB shuffle enable.

Set by the user to 1 to enable

LSB shuffling.

Set by the user to 0 to disable

LSB shuffling.

IDACPD

IDAC power-down bit.

Set by the user to 1 to power

down the IDAC. IDAC output is

high impedance.

Set by the user to 0 to power

up the IDAC.

IDACCLK

IDAC update rate.

Set by the user to update the

IDAC using Timer1.

Cleared by the user to update

the IDAC using HCLK (core

clock).

IDACCLR

IDAC clear bit.

Set by the user to enable

normal IDAC operation.

Cleared by the user to reset

data register of the IDAC to 0.

Mode

Mode bit. This bit must always

be cleared.

Reserved

Set this bit to 0.

Table 63. TDSCON MMR Bit Designations

Bit(s)

Name

Setting

Description

[7:3]

Reserved

The user sets these bits to 0.

Reserved

The user must set this to 1.

DISINT

Disable thermal trigger interrupt.

Set by the user to 0 to generate

an interrupt if the temperature

passes the thermal shutdown

point.

DISSD

Set by the user to 0 to disable the

output current DACs when the

temperature passes a trip point.

Table 64. IDAC0PULLDOWN MMR Bit Designations

Bit(s)

Name

Setting

Description

[7:6]

Reserved

These bits are set to 0 by the

user.

Pulldown

IDAC0 pull-down.

Set to 1 by the user to pull

down the IDAC0 pin as well as

power down IDAC0.

Set to 0 by the user to disable

the pull-down.

PLA_PD_EN

PLA output trigger enable.

Set to 1 by the user to enable

the PLA output to trigger the

IDAC0 pull-down.

Set to 0 by the user to disable

this feature.

3:0

PLA Source

PLA output source for PLA

output trigger enable.

Can select the output of any

element, 0 to 15, by

programming these bits with

the corresponding binary

value.

Table 65. IDAC Data Registers (Default Value = 0x00000000,

Read and Write Access)

Name

Address (Hex)

IDAC0DAT

0xFFFF0704

IDAC1DAT

0xFFFF0710

IDAC2DAT

0xFFFF071C

IDAC3DAT

0xFFFF0728

IDAC4DAT

0xFFFF0734

Table 66. IDACxDAT MMR Bit Designations

Bit(s)

Name

Setting

Description

[31:28]

Reserved

These bits are reserved.

[27:17]

Data

Data from IDACx.

[16:0]

Reserved

000

These bits are reserved.

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