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ADUC7121BBCZ Datasheet(PDF) 13 Page - Analog Devices |
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ADUC7121BBCZ Datasheet(HTML) 13 Page - Analog Devices |
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13 / 102 page  Data Sheet ADuC7120/ADuC7121 Rev. D | Page 13 of 102 Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description Min1 Typ1 Max Unit t CS CS to the SPICLK edge2 200 ns tSL SPICLK low pulse width (SPIDIV + 1) × tUCLK ns tSH SPICLK high pulse width (SPIDIV + 1) × tUCLK ns tDAV Data output valid after SPICLK edge 25 ns tDSU Data input setup time before SPICLK edge 1 × tUCLK ns tDHD Data input hold time after SPICLK edge 2 × tUCLK ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSR SPICLK rise time 5 12.5 ns tSF SPICLK fall time 5 12.5 ns tSFS CS high after SPICLK edge 0 ns 1 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. 2 CS is the CS (SPI slave select input) function of the multifunction Pin F3. SPICLK (POLARITY = 0) CS SPICLK (POLARITY = 1) tSH tSL tSR tSF tSFS MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO BIT 1 LSB IN tDHD tDSU tDAV tDR tDF tCS Figure 5. SPI Slave Mode Timing (Phase Mode = 1) |
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