ADF4212LBRU datasheet(5/20 Pages) AD

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ADF4212L

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PIN FUNCTION DESCRIPTION

Mnemonic

Description

CPRF

RF Charge Pump Output. When enabled, this provides

±ICP to the external RF loop filter, which in turn drives the

external RF VCO.

DGNDRF

Digital Ground Pin for the RF Digital Circuitry

RFIN

Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.

AGNDRF

Ground Pin for the RF Analog Circuitry

FLO

Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k

Ω.

See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

DGNDIF

Digital Ground Pin for the IF Digital, Interface, and Control Circuitry

MUXOUT

This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF, or the scaled Reference Frequency

to be accessed externally.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.

RSET

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The

nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is

CP MAX

SET

13 5

so, with RSET = 2.7 k

Ω, ICP MAX = 5 mA for both the RF and IF Charge Pumps.

AGNDIF

Ground Pin for the IF Analog Circuitry

IFIN

Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.

CPIF

Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO.

VP2Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where VDD2 is 3 V,

it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

VDD2Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be placed

as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the same

potential as VDD1.

VDD1Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible to

this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2.

VP1Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where VDD1 is 3 V,

it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

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