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ADF4212LBRU Datasheet(PDF) 11 Page - Analog Devices |
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ADF4212LBRU Datasheet(HTML) 11 Page - Analog Devices |
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11 / 20 page  REV. 0 ADF4212L –11– Table I. C2, C1 Truth Table Control Bits C2 C1 Data Latch 00 IF R Counter 01 IF N Counter (A and B) 10 RF R Counter 11 RF N Counter (A and B) Table II. Latch Summary 15-BIT REFERENCE COUNTER CONTROL BITS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 C1 (0) C2 (0) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 P2 P3 P4 IF R COUNTER LATCH P1 IF CP CURRENT SETTING DB23 IFCP2 DB22 IFCP1 DB21 IFCP0 R15 12-BIT B COUNTER CONTROL BITS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 C1 (1) C2 (0) A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 B7 B8 B11 B12 P5 IF N COUNTER LATCH B10 IF PRESCALER DB23 P8 DB22 P7 DB21 P6 B9 6-BIT A COUNTER 15-BIT RF REFERENCE COUNTER CONTROL BITS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 C1 (0) C2 (1) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 P10 P11 P12 RF R COUNTER LATCH P9 RF CP CURRENT SETTING DB23 RFCP2 DB22 RFCP1 DB21 RFCP0 R15 12-BIT B COUNTER CONTROL BITS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 C1 (1) C2 (1) A1 A2 A3 A4 A5 A6 B1 B2 B3 B4 B5 B6 B7 B8 B11 B12 P14 RF N COUNTER LATCH B10 RF PRESCALER DB23 P17 DB22 P16 DB21 P15 B9 6-BIT A COUNTER RF/IF Input Shift Register The ADF4212L digital section includes a 24-bit input shift register, a 14-bit IF R counter, and an 18-bit IF N counter (com- prising a 6-bit IF A counter and a 12-bit IF B counter). Also present is a 14-bit RF R counter and an 18-bit RF N counter (comprising a 6-bit RF A counter and a 12-bit RF B counter). Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1, and DB0, as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table VI. Table I shows a summary of how the latches are programmed. |
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