DS2152 datasheet(13/97 Pages) MAXIM

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DS2152

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NAME

FUNCTION

RLOS/LOTC

Receive Loss of Sync/Loss of Transmit Clock. A dual function output that is

controlled by the CCR3.5 control bit. This pin can be programmed to either toggle high

when the synchronizer is searching for the frame and multiframe or to toggle high if the

TCLK pin has not been toggled for 5

µs.

RCL

Receive Carrier Loss. Set high when the line interface detects a loss of carrier.

RSIGF

Receive Signaling Freeze. Set high when the signaling data is frozen via either

automatic or manual intervention. Used to alert downstream equipment of the condition.

8MCLK

8MHz Clock. A 8.192MHz output clock that is referenced to the clock that is output at

the RCLK pin and is used to clock data through the receive side framer.

RPOSO

Receive Positive Data Output. Updated on the rising edge of RCLKO with the bipolar

data out of the line interface. This pin is normally tied to RPOSI.

RNEGO

Receive Negative Data Output. Updated on the rising edge of RCLKO with the bipolar

data out of the line interface. This pin is normally tied to RNEGI.

RCLKO

Receive Clock Output. Buffered recovered clock from the T1 line. This pin is normally

tied to RCLKI.

RPOSI

Receive Positive Data Input. Sampled on the falling edge of RCLKI for data to be

clocked through the receive side framer. RPOSI and RNEGI can be tied together for a

NRZ interface. Can be internally connected to RPOSO by tying the LIUC pin high.

RNEGI

Receive Negative Data Input. Sampled on the falling edge of RCLKI for data to be

clocked through the receive side framer. RPOSI and RNEGI can be tied together for a

NRZ interface. Can be internally connected to RNEGO by tying the LIUC pin high.

RCLKI

Receive Clock Input. Clock used to clock data through the receive side framer. This pin

is normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC

pin high.

2.3 Parallel Control Port Pins

NAME

FUNCTION

INT

Interrupt. Flags host controller during conditions and change of conditions defined in

the Status Registers 1 and 2 and the FDL Status Register. Active-low, open-drain

output.

TEST

Tri-State Control. Set high to tri-state all output and I/O pins (including the parallel

control port). Set low for normal operation. Useful in board-level testing.

MUX

Bus Operation. Set low to select nonmultiplexed bus operation. Set high to select

multiplexed bus operation.

56–65

D0–D7/

AD0–AD7

Data Bus or Address/Data Bus. In nonmultiplexed bus operation (MUX = 0), serves as

the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed

address/data bus.

66–72

A0–A6

Address Bus. In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In

multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.

BTS

Bus Type Select. Strap high to select Motorola bus timing; strap low to select Intel bus

timing. This pin controls the function of the RD ( DS ), ALE(AS), and WR (R/ W ) pins.

If BTS = 1, then these pins assume the function listed in parentheses.

RD(DS)

Read Input (Data Strobe). RD and DS are active-low signals when MUX = 1. DS is

active high when MUX = 0. See bus timing diagrams.

Chip Select. Must be low to read or write to the device. CS is an active-low signal.

ALE(AS)

A7 or Address Latch Enable (Address Strobe). In non-multiplexed bus operation

(MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1),

serves to demultiplex the bus on a positive-going edge.

WR(R/W)

Write Input (Read/Write). WR is an active-low signal.

DS2152 Datasheet(PDF) 13 Page - Maxim Integrated Products

DS2152 Datasheet(HTML) 13 Page - Maxim Integrated Products

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