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DS2152 Datasheet(PDF) 54 Page - Maxim Integrated Products |
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DS2152 Datasheet(HTML) 54 Page - Maxim Integrated Products |
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54 / 97 page  DS2152 54 of 97 10 CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in Fractional T1 or ISDN-PRI applications. When the appropriate bits are set to 1, the RCHBLK and TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in Section 16 for an example. RCBR1/RCBR2/RCBR3: RECEIVE CHANNEL BLOCKING REGISTERS (Address = 6C to 6E Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 RCBR1 (6C) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 RCBR2 (6D) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 RCBR3 (6E) SYMBOL POSITION NAME AND DESCRIPTION CH24 RCBR3.7 Receive Channel Blocking Registers. 0 = force the RCHBLK pin to remain low during this channel time CH1 RCBR1.0 1 = force the RCHBLK pin high during this channel time TCBR1/TCBR2/TCBR3: TRANSMIT CHANNEL BLOCKING REGISTERS (Address = 32 to 34 Hex) (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TCBR1 (32) CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TCBR1 (33) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TCBR1 (34) SYMBOL POSITION NAME AND DESCRIPTION CH24 TCBR3.7 Transmit Channel Blocking Registers. 0 = force the TCHBLK pin to remain low during this channel time CH1 TCBR1.0 1 = force the TCHBLK pin high during this channel time |
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