DS2152 datasheet(14/97 Pages) MAXIM

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DS2152

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2.4 Line Interface Pins

NAME

FUNCTION

MCLK

Master Clock Input. A 1.544MHz (±50ppm) clock source with TTL levels is applied at

this pin. This clock is used internally for both clock/data recovery and for jitter

attenuation. A quartz crystal of 1.544MHz may be applied across MCLK and XTALD

instead of the TTL level clock source.

XTALD

Quartz Crystal Driver. A quartz crystal of 1.544MHz may be applied across MCLK

and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a

TTL clock source is applied at MCLK.

8XCLK

Eight Times Clock. A 12.352MHz clock that is frequency locked to the 1.544MHz

clock provided from the clock/data recovery block (if the jitter attenuator is enabled on

the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit

side). Can be internally disabled via the TEST2 register if not needed.

LIUC

Line Interface Connect. Tie low to separate the line interface circuitry from the

framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/

RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter

circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When

LIUC is tied high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be

tied low.

16, 17

RTIP,

RRING

Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect

via a 1:1 transformer to the T1 line. See Section 15 for details.

29, 32

TTIP,

TRING

Transmit Tip and Ring. Analog line driver outputs. These pins connect via a 1:1.15 or

1:1.36 step-up transformer to the T1 line. See Section 15 for details.

2.5 Supply Pins

NAME

FUNCTION

44, 61,

81, 83

DVDD

Digital Positive Supply. 5.0V ±5%. Should be tied to the RVDD and TVDD pins.

RVDD

Receive Analog Positive Supply. 5.0V ±5%. Should be tied to the DVDD and TVDD

pins.

TVDD

Transmit Analog Positive Supply. 5.0V ±5%. Should be tied to the RVDD and DVDD

pins.

45, 60,

80, 84

DVSS

Digital Signal Ground. Should be tied to the RVSS and TVSS pins.

19, 20,

RVSS

Receive Analog Signal Ground. 0V. Should be tied to the DVSS and TVSS pins.

TVSS

Transmit Analog Ground. 0V. Should be tied to the RVSS and DVSS pins.

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