ADM1272 datasheet(39/57 Pages) AD

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Data Sheet

ADM1272

Rev. B | Page 39 of 57

Multiple Devices on Bus

When there are multiple devices on the bus, the processor issues

an SMBus alert response address (ARA) command to find out

which device asserted the SMBus alert line. The processor reads the

status bytes from that device and issues a CLEAR_FAULTS

command.

SMBUS ALERT RESPONSE ADDRESS

The SMBus ARA is a special address that can be used by the

bus host to locate any devices that must communicate with the

bus host. A host typically uses a hardware interrupt pin to

monitor the SMBus alert pins of multiple devices. When the

host interrupt occurs, the host issues a message on the bus

using the SMBus receive byte or receive byte with PEC

protocol.

The special address used by the host is 0x0C. Any devices that

have an SMB alert signal return their own 7-bit address as the

seven MSBs of the data byte. The LSB value is not used and can

be either 1 or 0. The host reads the device address from the

received data byte and proceeds to handle the alert condition.

More than one device can have an active SMB alert signal and

attempt to communicate with the host. In this case, the device

with the lowest address dominates the bus and succeeds in

transmitting its address to the host. The device that succeeds

disables its SMBus alert signal. If the host sees that the SMBus alert

signal is still low, it continues to read addresses until all devices that

must communicate have transmitted their addresses.

EXAMPLE USE OF SMBus ARA

The full sequence of steps that occurs when an SMBus alert is

generated and cleared is as follows:

A fault or warning is enabled using the ALERT2_CONFIG

command, and the corresponding status bit for the fault or

warning changes from 0 to 1, indicating that the fault or

warning has just become active.

The GPO2/ALERT2 pin becomes active (set low) to signal

that an SMBus alert is active.

The host processor issues an SMBus ARA command to

determine which device has an active alert.

If there are no other active alerts from devices with lower

I2C addresses, this device makes the GPO2/ALERT2 pin

inactive (set high) during the no acknowledge bit period

after it sends its address to the host processor.

If the GPO2/ALERT2 pin stays low, the host processor

must continue to issue SMBus ARA commands to devices

to determine the addresses of all devices that require a

status check.

The ADM1272 continues to operate with the GPO2/ALERT2

pin inactive and the contents of the status bytes unchanged

until the host reads the status bytes and clears them, or

until a new fault occurs. If a status bit for a fault/warning

that is enabled on the GPO2/ALERT2 pin and that was not

already active (equal to 1) changes from 0 to 1, a new alert

is generated, causing the GPO2/ALERT2 pin to become

active again.

DIGITAL COMPARATOR MODE

The GPO1/ALERT1/CONV and GPO2/ALERT2 pins can be

configured to indicate if a user defined threshold for voltage,

current, power, or temperature is exceeded. In this mode, the

output pin is live and is not latched when a warning threshold

is exceeded. In effect, the pin acts as a digital comparator, where

the threshold is set using the warning limit threshold commands.

The ALERTx_CONFIG command is used, similar to the SMBus

alert configuration, to select the specific warning threshold to be

monitored. The GPO1/ALERT1/CONV or GPO2/ALERT2 pin.

ADM1272 Datasheet(PDF) 39 Page - Analog Devices

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