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Data Sheet

ADM1272

Rev. B | Page 13 of 57

Pin No.

Mnemonic

Description

ESTART

FET Energy Tracking During Power-Up. This pin approximates the energy in the FET during

power-up. The user can place a component network between the ESTART pin and ground that

allows the pin voltage to be proportional to the predicted MOSFET junction temperature. If the

voltage on the pin exceeds a threshold (1 V), the FET is deemed to be running too close to its

SOA and is turned off. This setting assumes lower current limits and greater SOA capability.

EFAULT

FET Energy Tracking During Normal Operation. This pin approximates the energy in the FET

when faults occur during normal operation. The user can place a component network between

the EFAULT pin and ground that allows the pin voltage to be proportional to the predicted

MOSFET junction temperature. If the voltage on the pin exceeds a threshold (1 V), the FET is

deemed to be running too close to its SOA and is turned off. This setting assumes higher current

limits and lesser SOA capability. Considerations must be made if varying ISET with VIN/VOUT when

assuming constant current limits.

ENABLE

Enable Input. This pin is a digital logic input. This input must be high to allow the ADM1272 hot

swap controller to begin a power-up sequence. If this pin is held low, the ADM1272 is prevented

from powering up.

7, 8

ADR0, ADR1

PMBus Address. These pins can be tied to GND, tied to VCAP, left floating, or tied low through a

resistor for a total of 16 unique PMBus device addresses (see the Device Addressing section).

SCL

Serial Clock Pin. SCL is an open-drain input. It requires an external pull-up resistor.

SDAI

PMBus Serial Data Input. The serial data is split into an input and an output for easy use with

isolators.

SDAO

PMBus Serial Data Output. The serial data is split into an input and an output for easy use with

isolators.

MCB

Mask Circuit Breaker. When the voltage on this pin is greater than the threshold, the SOC

shutdown is disabled. The function returns immediately after the voltage returns below this

threshold.

GPIO2/ALERT2

General-Purpose Digital Input/Output 2 (GPIO2).

Alert (ALERT2). This pin can be configured to generate an alert signal when one or more fault or

warning conditions are detected. It is also possible to read the state of this pin on the PMBus.

This pin defaults to an alert output at power-up. There is no internal pull-up circuit.

GPIO1/ALERT1/CONV

General-Purpose Digital Input/Output 1 (GPIO1).

Alert (ALERT1). This pin can be configured to generate an alert signal when one or more fault or

warning conditions are detected.

Conversion (CONV). This pin can be used as an input signal to control when a power monitor

ADC sampling cycle begins. It is also possible to read the state of this pin on the PMBus.

This pin defaults to an alert output at power-up. There is no internal pull-up circuit on this pin.

FAULT

Fault. This pin asserts low and latches when a fault occurs. The faults that can trigger this pin are

an OC fault resulting in the EFAULT/ESTART threshold, an overtemperature fault, or a FET health

fault.

RESTART

Falling Edge Triggered Automatic Restart. The gate remains off for 10 sec by default, and then

powers back on. The device has an internal weak pull-up circuit to VCAP. This pin is also used to

configure the desired retry scheme. See the Hot Swap Retry section for additional details. The

default time for this function is 10 sec. However, this time can be adjusted from 0.1 sec to

25.6 sec by writing to the RESTART_TIME register.

PWRGD

Power-Good Signal. This pin indicates that the supply is within tolerance (PWGIN input), no

faults are detected, and the ADM1272 hot swap is enabled with the gate fully enhanced.

PWGIN

Power-Good Input Threshold. This pin sets the power-good input threshold. The user can set an

accurate power-good threshold with a resistor divider from the source of the FET (VOUT). The

PWRGD output signal is not asserted until the output voltage is above the threshold set by PWGIN.

GND

Ground.

20 to 24

No Connect. The NC pins are not required to be connected, but do have internal connections.

They share the same electrical node internally to the EPVCC pad and can therefore be used as a

thermal exit route from EPVCC on the same outer layer and same electrical connection as

EPVCC.

25 to 28, 33 to

37, 40

DNC

Do Not Connect. The DNC pins must not be connected to any electrical signal, GND, or supply

voltage. Any connect copper must be electrically isolated and appropriately spaced from other

nodes, which allows compliance with IPC-9592 recommendations for 80 V.

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