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ADM1272

Data Sheet

Rev. B | Page 24 of 57

SAFE OPERATING AREA PROTECTION

(ESTART/EFAULT)

The ADM1272 features an FET protection scheme that offers

increased flexibility for managing various system conditions

while still protecting the FET from SOA stress.

Traditional timer schemes uses a single fault timer to protect

the FET when regulating current or when current limits are

exceeded. This approach requires the timers to be set to worst

case conditions like short circuits, which limits the robustness

of the solution to various system conditions/faults.

For short circuits, the SOA requires the setting of a short timer

because the FET VDS is very high. However, for a load fault that

results in only a few volts across the FET VDS, because the timer

is optimized for worst case conditions, the timer setting remains

very short. If a transient fault occurs, resulting in a momentary

active current limit but only a few volts of VDS, the system is

likely to shut down quickly even though the FET SOA is not

exceeded because VDS is low and can operate longer. This

condition is problematic during common scenarios such as

input line steps and disturbances.

To accommodate these conditions and ensure there are no

unnecessary shutdowns, the ADM1272 monitors and uses the

FET VDS to optimize how long the FET is allowed to remain in

regulation. The ESTART and EFAULT pins control this regulation

time for start-up mode and normal mode, respectively. Each

pin programs an independent setting for each mode of

operation to allow SOA protection to be optimized for its

respective current limit. As the system transitions from one

mode to another, the ADM1272 retains any potential recent

SOA stress history by copying the same voltage from the

ESTART pin to the EFAULT pin at transitions and vice versa.

The assumption is that, although there is a significant level of

VDS across the FET, its drain current, ID, is being held constant

(at the limit); thus, the FET power is proportional to VDS. The

SOA curve of the FET indicates the amount the FET can dissipate,

for a given time, before the junction temperature reaches its

maximum and SOA is breached. A current source (IVDS)

equivalent to 1 μA per 1 V VDS is sourced from

EFAULT/ESTART. Through analysis and manipulations of the

SOA curves, for a given fixed current, an RC configuration from

EFAULT/ESTART to GND can provide a solution to ensure

the voltage on the pin reaches 1 V before the SOA is exceeded.

This configuration presents a profile on the EFAULT/ESTART

pin that is representative of the FET junction temperature.

Upon reaching 1 V, the device deems the FET to be at the SOA

limit and latches off. This solution results in fault on times that

are proportional to VDS and allows low VDS faults to recover

without latching off, while ensuring high VDS faults are latched

off immediately.

Although the EFAULT and ESTART pins provide the same

function for their respective operation mode, there is one subtle

difference: the ESTART pin enables IVDS only when the current

exceeds ICB, whereas the EFAULT IVDS is solely dependent on VDS.

A pull-down current of 500 nA discharges the RC network,

which allows a single capacitor on each pin to be used at the

expense of being able to use less of the SOA. When the current

control loop is near regulation, this 500 nA pull-down current

is disabled and a 1 μA pull-up current enabled. The 1 μA

current ensures that the EFAULT and ESTART pins run

current even if there is a very small VDS, thus allowing the

system to power down if this condition lasts for an extended

period. If conditions prevent the pins from reaching 1 V while at

a low VDS (where the SOA may indicate dc), there is an internal

100 ms limit, after which the system returns a fault and latches

off. This backup limit prevents overheating in a steady state in

the MOSFET. The 100 ms timer runs when VGS is <10 V and

the current is in regulation.

FET GATE DRIVE

The ADM1272 is designed to control a high-side gate drive of

an external N channel FET. The GATE pin is driven by the FET

drive controller, which uses a charge pump to provide a pull-up

current to charge the FET gate pin. The FET drive controller

regulates to a maximum load current by regulating the GATE

pin. GATE is held to the VOUT pin when the supply is below

the UVLO limit.

The GATE pin features a GM amplifier output that sources and

sinks the GATE node to regulate the current. When a

shutdown is requested, the GATE pin uses a 10 mA pull-down

device to disable the FET and this pull-down device remains

active when the FET is disabled.

The charge pump used on the GATE pin is capable of driving

VGS to >10 V, but it is clamped to less than 14 V above VOUT.

These clamps ensure that the maximum VGS rating of the FET is

not exceeded.

FAST RESPONSE TO SEVERE OVERCURRENT

The ADM1272 features a separate high bandwidth current

sense amplifier that detects a severe overcurrent indicative of a

short-circuit condition. A fast response time allows the ADM1272

to handle events of this type that may otherwise cause catastrophic

damage if not detected and prevented quickly. The fast

response circuit ensures that the ADM1272 can detect an

overcurrent event at approximately 150% to 400% (default 200%)

of the normal current limit set by the ISET pin, and can

respond to and control the current within 1 μs in most cases.

There are four severe overcurrent threshold options and four

severe overcurrent glitch filter options selectable via the PMBus

registers as follows:



Thresholds: 150%, 200%, 300%, 400%



Glitch filters: 500 ns, 1 μs, 5 μs, 10 μs

The GATE pin of the ADM1272 is pulled down with ~1.5 A for

a maximum duration of 10 μs. Following a severe OC shutdown,

by default, the device attempts to regain control of the FET one

time. To expedite recovery after sudden shutdown events, a

gate boost circuit is enabled to bring the gate voltage back to

ADM1272 Datasheet(PDF) 24 Page - Analog Devices

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