LTC2949 datasheet(42/80 Pages) AD

42 / 80 page

LTC2949

Rev A

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Read-Write

DEF Default Value

Read Only

Signed Integer

Set Only (Note)

Unsigned Integer

Note: Write 1 to SO bits to request the associated action. Successful write can be checked by a read command directly following the write command. After

the action was performed the SO bit will be cleared automatically by LTC2949. Do not write to registers with SO bits, before all SO bits were read as 0. The

typical processing time per action is tIDLE_CORE or tCONT depending on operation mode, see related bit description for details.

MEMORY MAP AND PAGING MECHANISM

The memory map of the LTC2949 is organized in two pages, PAGE0 and PAGE1. PAGE0 contains all slow channel

result quantities, control and status registers while PAGE1 contains all threshold and configuration registers. Each

page has a register address space ranging from 0x00 to 0xEF, with each register consisting of one 8-bit byte of data.

Registers 0xF0 to 0xFF are common to both register pages. Register REGSCTRL at 0xFF is part of this range and is

used to switch between pages, see below. For clarity, all register addresses on PAGE1 are expressed as p1.0xYY in the

following while addresses on PAGE0 are simply referred to as 0xYY.

Multiple-byte data is stored with most significant byte at the lowest address (little-endian). For instance, the MSB

C1[47:40] of the quantity C1 is stored at address 0x00 in PAGE0.

Note that reading data from LTC2949's memory map (no matter if using direct command or indirect memory ac-

cess RDCV command with RDCVCONF=0) reports MSBytes first, while reading fast conversion results via RDCV

(RDCVCONF=1) reports LSBytes first.

Some addresses in the register map are not used and are reserved. Bits in non-reserved registers that are not explic-

itly described are also reserved. Writing to unused reserved registers or reserved bits in non-reserved registers may

result in unwanted behavior of the LTC2949, reserved bits in non-reserved registers should be written as 0; reading of

unused registers is generally harmless but will return random data. If software detection of device revision is neces-

sary, then contact the factory for details.

The Register Control Register (0xFF) selects the active memory page, allows to configure the LTC2949 to respond to

broadcast read commands, configures the RDCV command to indirect memory access mode and provides a memory

locking mechanism.

Table 23. Control Register REGSCTRL (0xFF)

BIT

SYMBOL

TYPE

DEFAULT

OPERATION

PAGE

Memory Map Page Select

0: PAGE0 of the memory map is selected.

1: PAGE1 of the memory map is selected.

BCREN

Broadcast Read Enable

0: LTC2949 does not respond to broadcast read commands

1: LTC2949 responds to broadcast read commands

[5:4]

MLK[1:0]

Memory Lock

00: Memory not locked

01: Memory lock requested by master

10: Memory locked

RDCVCONF

RDCV Configuration Bit

0: Indirect memory access mode. RDCV will report data starting at address written to

RDCVIADDR (0xFC).

1: RDCV command will report latest fast channel conversion results.

LTC2949 Datasheet(PDF) 42 Page - Analog Devices

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