P87LPC779 datasheet(62/74 Pages) PHILIPS

62 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

62 of 74

9397 750 13213

A special user data area is also available for access via the MOVC instruction at

addresses FCE0h through FCFFh. This ‘customer code’ space is programmed in the

same manner as the main code EPROM and may be used to store a serial number,

manufacturing date, or other application information.

8.18.1

System conﬁguration bytes

A number of user conﬁgurable features of the P87LPC779 must be deﬁned at power

up and therefore cannot be set by the program after start of execution. Those

features are conﬁgured through the use of two EPROM bytes that are programmed in

the same manner as the EPROM program space. The contents of the two

conﬁguration bytes, UCFG1 and UCFG2, are shown in Tables 48, 49, 51 and 52. The

values of these bytes may be read by the program through the use of the MOVX

instruction at the addresses shown in the tables.

Table 48:

UCFG1 - EPROM system conﬁguration byte 1 register (address FD00H) bit

allocation

Unprogrammed value: FFH

Bit

Symbol

WDTE

RPD

PRHI

BOV

CLKR

FOSC2

FOSC1

FOSC0

Table 49:

UCFG1 - EPROM system conﬁguration byte 1 register (address FD00H) bit

description

Bit

Symbol

Description

WDTE

Watchdog timer enable. When programmed (0), disables the

Watchdog timer. The timer may still be used to generate an

interrupt.

RPD

Reset pin disable. When programmed (0), disables the reset

function of pin P1.5, allowing it to be used as an input only port

pin.

PRHI

Port reset high. When ‘1’, ports reset to a high state. When ‘0’,

ports reset to a low state.

BOV

Brownout voltage select. When ‘1’, the brownout detect voltage is

2.5 V. When ‘0’, the brownout detect voltage is 3.8 V. This is

described in Section 8.11 “Power monitoring functions” on page

37.

CLKR

Clock rate select. When ‘0’, the CPU clock rate is divided by 2.

This results in machine cycles taking 12 CPU clocks to complete

as in the standard 80C51. For full backward compatibility, this

division applies to peripheral timing as well.

2 to 0

FOSC[2:0]

CPU oscillator type select. See Section 8.10 “Oscillator” on page

34 for additional information. Combinations other than those

shown below should not be used. They are reserved for future

use.

Table 50:

FOSC2-FOSC0 oscillator conﬁguration

FOSC2-FOSC0

Oscillator conﬁguration

1 1 1

External clock input on X1 (default setting for an unprogrammed

part).

0 1 1

Internal RC oscillator, 6 MHz.

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