P87LPC779 datasheet(26/74 Pages) PHILIPS

26 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

26 of 74

9397 750 13213

Values to be used in the CT1 and CT0 bits are shown in Table 18. To allow the

I2C-bus to run at the maximum rate for a particular oscillator frequency, compare the

actual oscillator rate to the fosc max column in the table. The value for CT1 and CT0 is

found in the ﬁrst line of the table where CPU clock max is greater than or equal to the

actual frequency. Table 18 also shows the machine cycle count for various settings of

CT1/CT0. This allows calculation of the actual minimum high and low times for SCL

as follows:

(3)

For instance, at an 8 MHz frequency, with CT1/CT0 set to 1 0, the minimum SCL high

and low times will be 5.25

µs. Table 18 also shows the Timer I timeout period (given

in machine cycles) for each CT1/CT0 combination. The timeout period varies

because of the way in which minimum SCL high and low times are measured. When

the I2C-bus interface is operating, Timer I is pre-loaded at every SCL transition with a

value dependent upon CT1/CT0. The pre-load value is chosen such that a minimum

SCL high or low time has elapsed when Timer I reaches a count of 008 (the actual

value pre-loaded into Timer I is 8 minus the machine cycle count).

TIRUN

Writing a ‘1’ to this bit lets Timer I run; a ‘0’ stops and clears it.

Together with SLAVEN, MASTRQ, and MASTER, this bit

determines operational modes as shown in Table 17.

3, 2

Reserved for future use. Should not be set to ‘1’ by user programs.

1, 0

CT1, CT0

These two bits are programmed as a function of the CPU clock

rate, to optimize the MIN HI and LO time of SCL when this device

is a master on the I2C-bus. The time value determined by these

bits controls both of these parameters, and also the timing for stop

and start conditions.

Table 17:

Interaction of TIRUN with SLAVEN, MASTRQ, and MASTER

SLAVEN,

MASTRQ,

MASTER

TIRUN

OPERATING MODE

All 0

The I2C-bus interface is disabled. Timer I is cleared and

does not run. This is the state assumed after a reset. If

an I2C-bus application wants to ignore the I2C-bus at

certain times, it should write SLAVEN, MASTRQ, and

TIRUN all to zero.

All 0

The I2C-bus interface is disabled.

Any or all 1

The I2C-bus interface is enabled. The 3 low-order bits

of Timer I run for min-time generation, but the hi-order

bits do not, so that there is no checking for I2C-bus

being ‘hung.’ This conﬁguration can be used for very

slow I2C-bus operation.

Any or all 1

The I2C-bus interface is enabled. Timer I runs during

frames on the I2C-bus, and is cleared by transitions on

SCL, and by Start and Stop conditions. This is the

normal state for I2C-bus operation.

Table 16:

I2CFG - I2C-bus conﬁguration register (address C8h) bit description

Bit

Symbol

Description

SCL min high/low time (in microseconds)

6 * min time count

CPUclock (in MHz)

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