SH7041A datasheet(570/923 Pages) RENESAS

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14.4

SCI Interrupt Sources and the DMAC/DTC

The SCI has four interrupt sources: transmit-end (TEI), receive-error (ERI), receive-data-full

(RxI), and transmit-data-empty (TxI). Table 14.12 lists the interrupt sources and indicates their

priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in the serial

control register (SCR). Each interrupt request is sent separately to the interrupt controller.

TxI is requested when the TDRE bit in the SSR is set to 1. TxI can start the direct memory access

controller (DMAC) or the data transfer controller (DTC) to transfer data. TDRE is automatically

cleared to 0 when the DMAC or the DTC writes data in the transmit data register (TDR).

RxI is requested when the RDRF bit in the SSR is set to 1. RxI can start the DMAC or the DTC to

transfer data. RDRF is automatically cleared to 0 when the DMAC or the DTC reads the receive

data register (RDR).

ERI is requested when the ORER, PER, or FER bit in the SSR is set to 1. ERI cannot start the

DMAC or the DTC.

TEI is requested when the TEND bit in the SSR is set to 1. TEI cannot start the DMAC or the

DTC. Where the TxI interrupt indicates that transmit data writing is enabled, the TEI interrupt

indicates that the transmit operation is complete.

Table 14.12 SCI Interrupt Sources

Interrupt Source

Description

DMAC/DTC Activation

Priority

ERI

Receive error (ORER, PER, or FER)

High

RxI

Receive data full (RDRF)

Yes

TxI

Transmit data empty (TDRE)

Yes

TEI

Transmit end (TEND)

Low

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