SH7041A datasheet(26/923 Pages) RENESAS

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Section 8

Data Transfer Controller (DTC)................................................................. 133

8.1

Overview............................................................................................................................ 133

8.1.1

Features................................................................................................................. 133

8.1.2

Block Diagram...................................................................................................... 134

8.1.3

8.2

Register Description .......................................................................................................... 135

8.2.1

DTC Mode Register (DTMR) .............................................................................. 135

8.2.2

DTC Source Address Register (DTSAR)............................................................. 138

8.2.3

DTC Destination Address Register (DTDAR)..................................................... 138

8.2.4

DTC Initial Address Register (DTIAR) ............................................................... 139

8.2.5

DTC Transfer Count Register A (DTCRA) ......................................................... 139

8.2.6

DTC Transfer Count Register B (DTCRB) .......................................................... 140

8.2.7

DTC Enable Registers (DTER) ............................................................................ 140

8.2.8

DTC Control/Status Register (DTCSR) ............................................................... 141

8.2.9

DTC Information Base Register (DTBR)............................................................. 143

8.3

Operation ........................................................................................................................... 143

8.3.1

Overview of Operation ......................................................................................... 143

8.3.2

Activating Sources................................................................................................ 145

8.3.3

DTC Vector Table ................................................................................................ 145

8.3.4

8.3.5

Normal Mode........................................................................................................ 149

8.3.6

Repeat Mode......................................................................................................... 149

8.3.7

Block Transfer Mode ............................................................................................ 150

8.3.8

Operation Timing ................................................................................................. 151

8.3.9

DTC Execution State Counts................................................................................ 151

8.3.10 DTC Usage Procedure .......................................................................................... 153

8.3.11 DTC Use Example................................................................................................ 153

8.4

Cautions on Use................................................................................................................. 154

Section 9

Cache Memory (CAC) .................................................................................. 155

9.1

Overview............................................................................................................................ 155

9.1.1

Features................................................................................................................. 155

9.1.2

Block Diagram...................................................................................................... 156

9.1.3

9.2

Register Explanation.......................................................................................................... 157

9.2.1

Cache Control Register (CCR) ............................................................................. 157

9.3

Address Array and Data Array .......................................................................................... 158

9.3.1

Cache Address Array Read/Write Space .............................................................. 159

9.3.2

Cache Data Array Read/Write Space ................................................................... 159

9.4

Cautions on Use................................................................................................................. 160

9.4.1

Cache Initialization............................................................................................... 160

9.4.2

Forced Access to Address Array and Data Array................................................. 160

9.4.3

Cache Miss Penalty and Cache Fill Timing ......................................................... 160

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