SH7041A datasheet(19/923 Pages) RENESAS

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Section

Page

Description

Appendix C Pin

States

Table C.1 Pin

Modes During Reset,

Power-Down, and

Bus Right Release

Modes (144 Pin)

(cont)

866

Table amended

Pin modes

Pin Function

Reset

Power-Down Bus Right

Standby in Bus

Class

Pin Name

Power-OnManual

Standby Sleep Release

Right Release

MTU

TIOC0A–TIOC0D,

TIOC1A–TIOC1D,

TIOC2A–TIOC2D,

TIOC3A, TIOC3C

I/O

TIOC3B,TIOC3D,

TIOC4A–TIOC4D

I/O

TCLKA–TCLKD

Port

control

POE0–POE3

SCI

SCK0–SCK1

I/O

TXD0–TCD1

OO*

RXD0–RXD1

A/D

ADTRG

converter AN0–AN7

I/O Port

PA0–PA23

I/O

PB0–PB9

PC0–PC15

PD0–PD31

PE0–PE8,PE10

PE9,PE11–PE15

I/O

PF0–PF17

Notes: 1. There are instances where bus right release and transition to software standby mode

occur simultaneously due to the timing between

BREQ and internal operations. In such

cases, standby mode results, but the standby state may be different.

The initial pin states depend on the mode. See section 18, Pin Function Controller

(PFC), for details.

2. I: Input, O: Output, H: High-level output, L: Low-level output, Z: High impedance,

K: Input pin with high impedance, output pin mode maintained.

*1 If the standby control register port high-impedance bits are set to 1, output pins become

high impedance.

*2 A21–A18 will become input ports after power-on reset.

*3 Input in the SH7044/SH7045 F-ZTAT version.

*4 General use I/O ports PAn, PBn, PCn, PDn, and PEn, as well as pins multiplexed with

them, are unstable during the

RES setup time (tRESS) immediately after the RES pin

goes to low level.

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