SH7041A datasheet(29/923 Pages) RENESAS

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vii

12.2.1 Timer Control Register (TCR) ............................................................................. 283

12.2.2 Timer Mode Register (TMDR)............................................................................. 288

12.2.3 Timer I/O Control Register (TIOR) ..................................................................... 290

12.2.4 Timer Interrupt Enable Register (TIER)............................................................... 306

12.2.5 Timer Status Register (TSR) ................................................................................ 309

12.2.6 Timer Counters (TCNT)....................................................................................... 312

12.2.7 Timer General Register (TGR)............................................................................. 313

12.2.8 Timer Start Register (TSTR) ................................................................................ 313

12.2.9 Timer Synchro Register (TSYR) .......................................................................... 314

12.2.10 Timer Output Master Enable Register (TOER).................................................... 315

12.2.11 Timer Output Control Register (TOCR)............................................................... 317

12.2.12 Timer Gate Control Register (TGCR) .................................................................. 318

12.2.13 Timer Subcounter (TCNTS)................................................................................. 320

12.2.14 Timer Dead Time Data Register (TDDR) ............................................................ 321

12.2.15 Timer Period Data Register (TCDR) .................................................................... 321

12.2.16 Timer Period Buffer Register (TCBR) ................................................................. 322

12.3

Bus Master Interface .......................................................................................................... 322

12.3.1 16-Bit Registers .................................................................................................... 322

12.3.2 8-Bit Registers ...................................................................................................... 323

12.4

Operation ........................................................................................................................... 324

12.4.1 Overview............................................................................................................... 324

12.4.2 Basic Functions..................................................................................................... 325

12.4.3 Synchronous Operation ........................................................................................ 330

12.4.4 Buffer Operation................................................................................................... 333

12.4.5 Cascade Connection Mode ................................................................................... 336

12.4.6 PWM Mode .......................................................................................................... 337

12.4.7 Phase Counting Mode........................................................................................... 341

12.4.8 Reset-Synchronized PWM Mode ......................................................................... 348

12.4.9 Complementary PWM Mode ............................................................................... 352

12.5

Interrupts ............................................................................................................................ 377

12.5.1 Interrupt Sources and Priority Ranking ................................................................ 377

12.5.2 DTC/DMAC Activation ....................................................................................... 379

12.5.3 A/D Converter Activation..................................................................................... 379

12.6

Operation Timing............................................................................................................... 380

12.6.1 Input/Output Timing............................................................................................. 380

12.6.2 Interrupt Signal Timing ........................................................................................ 385

12.7

Notes and Precautions........................................................................................................ 389

12.7.1 Input Clock Limitations........................................................................................ 389

12.7.2 Note on Cycle Setting........................................................................................... 389

12.7.3 Contention between TCNT Write and Clear ........................................................ 390

12.7.4 Contention between TCNT Write and Increment................................................. 391

12.7.5 Contention between Buffer Register Write and Compare Match......................... 392

12.7.6 Contention between TGR Read and Input Capture .............................................. 394

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