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SH7041A Datasheet(PDF) 104 Page - Renesas Technology Corp

Part # SH7041A
Description  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7041A Datasheet(HTML) 104 Page - Renesas Technology Corp

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66
Table 2.13
Arithmetic Operation Instructions (cont)
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
DMULS.L Rm,Rn
0011nnnnmmmm1101
Signed operation of Rn
× Rm → MACH, MACL
32
× 32 → 64 bit
2 to 4*
DMULU.L Rm,Rn
0011nnnnmmmm0101
Unsigned operation of
Rn
× Rm → MACH,
MACL 32
× 32 → 64 bit
2 to 4*
DT
Rn
0100nnnn00010000
Rn – 1
→ Rn, when Rn
is 0, 1
→ T. When Rn is
nonzero, 0
→ T
1
Comparison
result
EXTS.B
Rm,Rn
0110nnnnmmmm1110
A byte in Rm is sign-
extended
→ Rn
1—
EXTS.W
Rm,Rn
0110nnnnmmmm1111
A word in Rm is sign-
extended
→ Rn
1—
EXTU.B
Rm,Rn
0110nnnnmmmm1100
A byte in Rm is zero-
extended
→ Rn
1—
EXTU.W
Rm,Rn
0110nnnnmmmm1101
A word in Rm is zero-
extended
→ Rn
1—
MAC.L
@Rm+,@Rn+
0000nnnnmmmm1111
Signed operation of
(Rn)
× (Rm) +MAC →
MAC 32
× 32 → 64 bit
3/(2 to
4)*
MAC.W
@Rm+,@Rn+
0100nnnnmmmm1111
Signed operation of
(Rn)
× (Rm) + MAC →
MAC 16
× 16 + 64 →
64 bit
3/(2)*
MUL.L
Rm,Rn
0000nnnnmmmm0111
Rn
× Rm → MACL, 32
× 32 → 32 bit
2 to 4*
MULS.W
Rm,Rn
0010nnnnmmmm1111
Signed operation of Rn
× Rm → MAC 16 × 16
→ 32 bit
1 to 3*
MULU.W
Rm,Rn
0010nnnnmmmm1110
Unsigned operation of
Rn
× Rm → MAC 16 ×
16
→ 32 bit
1 to 3*
NEG
Rm,Rn
0110nnnnmmmm1011
0–Rm
→ Rn
1
NEGC
Rm,Rn
0110nnnnmmmm1010
0–Rm–T
→ Rn, Borrow
→ T
1
Borrow



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