SH7041A datasheet(151/923 Pages) RENESAS

Part #	SH7041A

Description	Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)

PDF	923 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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113

Yes

NMI?

Yes

User break?

Yes

Level 15

interrupt?

Yes

I3 to I0

≤

level 14?

Yes

Level 14

interrupt?

Yes

I3 to I0

≤

level 13?

Yes

Level 1

interrupt?

Yes

I3 to I0 =

level 0?

Program

execution state

IRQOUT = low level*1

Save SR to stack

Save PC to stack

IRQOUT = high level*2

Branches to exception

service routine

I3 to I0: Interrupt mask bits of status register

Interrupt?

Copy accept-interrupt

level to I3 to I0

Reads exception

vector table

Notes: *1

IRQOUT is the same signal as the interrupt request signal to the CPU (see

figure 6.1). Thus, it is output when there is a higher priority interrupt request

than the one in the I3 to I0 bits of the SR.

When the accepted interrupt is sensed by edge, the

IRQOUT pin becomes

high level at the point when the CPU starts interrupt exception processing

instead of instruction execution (before SR is saved to the stack).

If the interrupt controller has accepted another interrupt with a higher priority

and has output an interrupt request to the CPU, the

IRQOUT pin will remain

low level.

Figure 6.3 Interrupt Sequence Flowchart

SH7041A Datasheet(PDF) 151 Page - Renesas Technology Corp

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