SH7041A datasheet(179/923 Pages) RENESAS

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141

For the A mask, overwrite this register as follows:

When clearing bit to 0: read the 1 bit to clear and write 0.

When setting bit to 1: read the 0 bit to set and write 1.

Bit:

DTE7

DTE6

DTE5

DTE4

DTE3

DTE2

DTE1

DTE0

Initial value:

R/W:

R/W*

Note: * DTER bits can only be modified by writing 1 after reading 0, or writing 0 after reading 1.

8.2.8

DTC Control/Status Register (DTCSR)

The DTCSR is a 16-bit readable/writable register that sets disable/enable for DTC activation by

software, as well as the DTC vector addresses for software activation. It also indicates the DTC

transfer status.

The DTCSR is initialized to H'0000 by power-on resets and in standby mode. Manual reset does

not initialize DTCSR.

Bit:

—

NMIF

SWDTE

Initial value:

R/W:

R/W*

Bit:

Bit name: DTVEC7 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0

Initial value:

R/W:

R/W*

Notes: *1 For the NMIF and AE bits, only a 0 write after a 1 read is possible.

*2 For the SWDTE bit, a 1 write is always possible, but a 0 write is possible only after a 1

is read.

*3 For the DTVEC7–DTVEC0 bits, writes are possible only when SWDTE = 0.

*4 Be sure to write 0 to the DTVEC0 bit.

Bits 15–11—Reserved: These bits always read as 0. The write value should always be 0.

SH7041A Datasheet(PDF) 179 Page - Renesas Technology Corp

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