| Electronic Components Datasheet Search |
|
LTM4622 Datasheet(PDF) 9 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
LTM4622 Datasheet(HTML) 9 Page - Analog Devices |
|
9 / 24 page ![]() LTM4663 9 Rev. A For more information www.analog.com + – LINEAR POWER STAGE PWM SWITCHING MODE REGULATOR CONTROL VREF/2 TEMPERATURE ERROR AMPLIFIER AV = RFB/(RTH + RX) – RFB/R +1 CHOPPER 1 + – PID COMPENSATION AMPLIFIER AV = Z2/Z1 CHOPPER 2 VREF TFB RX Z1 Z2 VTSET VLDR VPWM RTH TAMPOUT TSET PAMPN PAMPOUT TEC + – RFB R LTM4663 F02 below 0.07V, the controller goes into an ultralow current state. The current drawn in shutdown mode is 480µA typically. Most of the current is consumed by the VREF circuit block, which is always on even when the device is disabled or shut down. The device can also be enabled when an external synchronization clock signal is applied to the EN/SY pin, and the voltage at VLIM/SD input is above 0.07V. Table 1 shows the combinations of the two input signals that are required to enable the LTM4663. Table 1. Enable Pin Combinations EN/SY PIN VLIM/SD PIN STATUS >2.1V >0.07V Enable Clock >0.07V Enable <0.8V No Effect* Shutdown No Effect* <0.07V Shutdown *No effect means this signal has no effect in shutting down or in enabling the device. OPERATING FREQUENCY The LTM4663 has a default 2MHz switching frequency for the PWM switching regulator output stage. The oscillator is active when the enabled voltage at the EN/SY pin is set to a logic level higher than 2.1V and the VLIM/SD pin voltage is greater than the shutdown threshold of 0.07V. FREQUENCY SYNCHRONIZATION AND CLOCK IN The switching frequency of the LTM4663 can be syn- chronized to an external clock from 1.85MHz to 3.25MHz Figure 2. LTM4663 Control Signal Flow Chart APPLICATIONS INFORMATION applied to the EN/SY input pin. The clock high level must be above 2.1V and the clock low level below 0.8V. SOFT-START The LTM4663 has an internal soft-start circuit that gen- erates a ramp with a typical 150ms profile to minimize inrush current during power-up. The settling time and the final voltage across the TEC depends on the TEC voltage required by the control voltage of voltage loop. The higher the TEC voltage is, the longer it requires to reach the final output voltage. When the LTM4663 is first powered up, the linear side discharges the output of any prebias voltage. As soon as the prebias is eliminated, the soft-start cycle begins. During the soft-start cycle, both the PWM and linear out- puts track the internal soft-start ramp until they reach mid-scale VB. From the mid-scale voltage, the PWM and linear outputs are then diverge from each other until the required differential voltage is developed across the TEC or the differential voltage reaches the voltage limit. The voltage developed across the TEC depends on the control point at that moment. Figure 3 shows an example of the soft-start in cooling mode. Note that, as both the VLDR and VPWM voltages increase with the soft-start ramp and approach VB, the ramp slows down to avoid possible cur- rent overshoot at the point where the TEC voltage starts to build up. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |