LTC4366 datasheet(25/32 Pages) AD

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LTC7862

Rev 0

For more information www.analog.com

APPLICATIONS INFORMATION

If the timer reaches 2.19V, the LTC7862 is not allowed

to switch again until TMR is discharged down to 0.25V

by a 1.1µA current source. This sets a time period that

permits the switching surge stopper components to cool

down before attempting to switch again. This cooldown

period is given by:

TCOOLDOWN = (2.19V – 0.25V) • CTMR/1.1µA

After this cooldown period, the LTC7862 may try to switch

again. On this retry, the time spent switching is limited to

TRETRY = 1.94V • CTMR/40µA

During a sustained fault condition, this results in a retry

duty cycle that is to first order independent of CTMR and

is defined by:

D=100•TRETRY/(TCOOLDOWN+TRETRY)=100•1/36.4≈2.7%

Warning Indicator (WARNB)

The WARNB pin is connected to the open drain of an

internal N-channel MOSFET. The MOSFET turns on and

pulls the WARNB pin low to ground (GND) whenever the

LTC7862 is switching (i.e, not in dropout) during an over-

voltage or overcurrent fault or during startup. The WARNB

pin is also pulled low during shutdown and during the

cooldown period after a fault timeout. The MOSFET is

turned off and the WARNB pin enters a high-impedance

state 60µs after the LTC7862 enters normal operation

(dropout) with the top external MOSFET (TG) on con-

tinuously. The WARNB pin is normally pulled up by an

external resistor to a voltage source no greater than 6V.

Checking Transient Response

The regulator loop response can be checked by looking

at the load current transient response. Switching regula-

tors take several cycles to respond to a step in DC (resis-

tive) load current. When a load step occurs, VOUT shifts

by an amount equal to ∆ILOAD (ESR), where ESR is the

effective series resistance of COUT. ∆ILOAD also begins to

charge or discharge COUT generating the feedback error

signal that forces the regulator to adapt to the current

change and return VOUT to its steady-state value. During

this recovery time VOUT can be monitored for excessive

overshoot or ringing, which would indicate a stability

problem. OPTI-LOOP compensation allows the transient

response to be optimized over a wide range of output

capacitance and ESR values. The availability of the ITH pin

not only allows optimization of control loop behavior, but

it also provides a DC coupled and AC filtered closed-loop

response test point. The DC step, rise time and settling

at this test point truly reflects the closed-loop response.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin. The bandwidth

can also be estimated by examining the rise time at the

pin. The ITH external components shown in the first page

circuit will provide an adequate starting point for most

applications.

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

to optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of 1μs to

10μs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

Placing a power MOSFET directly across the output

capacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better to

look at the ITH pin signal which is in the feedback loop and

is the filtered and compensated control loop response.

The gain of the loop will be increased by increasing RC and

the bandwidth of the loop will be increased by decreas-

ing CC. If RC is increased by the same factor that CC is

decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual over-

all supply performance.

LTC4366 Datasheet(PDF) 25 Page - Analog Devices

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