LTC4366 datasheet(26/32 Pages) AD

26 / 32 page

LTC7862

Rev 0

For more information www.analog.com

APPLICATIONS INFORMATION

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • CLOAD. Thus a 10μF capacitor would

require a 250μs rise time, limiting the charging current

to about 200mA.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC.

1. Are the signal and power grounds kept separate?

The combined IC signal ground pin and the ground

return of CDRVCC must return to the combined COUT

(–) terminals. The path formed by the top N-channel

MOSFET, bottom N-channel MOSFET and the CIN

capacitor should have short leads and PC trace

lengths. The output capacitor (–) terminals should

be connected as close as possible to the (–) terminals

of the input capacitor by placing the capacitors next

to each other.

2. Does the LTC7862 VFB pin’s resistive divider con-

nect to the (+) terminal of COUT? The resistive divider

must be connected between the (+) terminal of COUT

and signal ground. The feedback resistor connections

should not be along the high current input feeds from

the input capacitor(s).

3. Are the SENSE– and SENSE+ leads routed together

with minimum PC trace spacing? The filter capacitor

between SENSE+ and SENSE– should be as close as

possible to the IC. Ensure accurate current sensing

with Kelvin connections at the SENSE resistor.

4. Is the DRVCC and decoupling capacitor connected

close to the IC, between the DRVCC and the ground

pin? This capacitor carries the MOSFET drivers’ cur-

rent peaks.

5. Keep the SW, TG, and BOOST nodes away from sensi-

tive small-signal nodes. All of these nodes have very

large and fast moving signals and therefore should be

kept on the output side of the LTC7862 and occupy

minimum PC trace area.

6. Use a modified star ground technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the DRVCC

decoupling capacitor, the bottom of the voltage feed-

back resistive divider and the GND pin of the IC.

PC Board Layout Debugging

It is helpful to use a DC-50MHz current probe to moni-

tor the current in the inductor while testing the circuit.

Monitor the output switching node (SW pin) to synchro-

nize the oscilloscope to the internal oscillator and probe

the actual output voltage as well. Check for proper per-

formance over the operating voltage and current range

expected in the application. The frequency of operation

should be maintained over the input voltage range down

to dropout and until the output load drops below the low

current operation threshold.

The duty cycle percentage should be maintained from

cycle to cycle in a well-designed, low noise PCB imple-

mentation. Variation in the duty cycle at a subharmonic

rate can suggest noise pickup at the current or volt-

age sensing inputs or inadequate loop compensation.

Overcompensation of the loop can be used to tame a

poor PC layout if regulator bandwidth optimization is not

required.

Reduce VIN from its nominal level to verify operation

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering VIN while

monitoring the output to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

LTC4366 Datasheet(PDF) 26 Page - Analog Devices

LTC4366 Datasheet(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL