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AMC1202 Datasheet(PDF) 9 Page - Texas Instruments |
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AMC1202 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 32 page ![]() 6.9 Electrical Characteristics (continued) minimum and maximum specifications apply from TA = – 55°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, INP = – 50 mV to + 50 mV, and INN = GND1; typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VDD1POR VDD1 power-on-reset threshold voltage VDD1 falling 2.4 2.6 2.8 V IDD1 High-side supply current 3.0 V ≤ VDD1 ≤ 3.6 V 6.2 8.5 mA 4.5 V ≤ VDD1 ≤ 5.5 V 7.2 9.8 IDD2 Low-side supply current 3.0 V ≤ VDD2 ≤ 3.6 V 5.3 7.2 4.5 V ≤ VDD2 ≤ 5.5 V 5.9 8.1 (1) The typical value includes one standard deviation ("sigma") at nominal operating conditions. (2) This parameter is input referred. (3) Offset error temperature drift is calculated using the box method, as described by the following equation: TCVOS = (ValueMAX - ValueMIN) / TempRange (4) Gain error temperature drift is calculated using the box method, as described by the following equation: TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106 6.10 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Output signal rise time 1.5 µs tf Output signal fall time 1.5 µs VINx to VOUTx signal delay (50% – 10%) unfiltered output 1 1.5 µs VINx to VOUTx signal delay (50% – 50%) unfiltered output 1.6 2.1 µs VINx to VOUTx signal delay (50% – 90%) unfiltered output 2.5 3 µs tAS Analog settling time VDD1 step to 3.0 V with VDD2 ≥ 3.0 V, to OUTP and OUTN valid, 0.1% settling 500 µs 6.11 Timing Diagram INP - INN OUTN 50% - 10% t f 50% - 50% 50% - 90% OUTP t r 50 mV 50 mV – 0 V CMout Figure 6-1. Rise, Fall, and Delay Time Waveforms www.ti.com AMC1202 SBASAB8 – MAY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: AMC1202 |
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