AWR2944 datasheet(42/93 Pages) TI

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8.11 Input Clocks and Oscillators

8.11.1 Clock Specifications

An external crystal is connected to the device pins. Figure 8-3 shows the crystal implementation.

40 MHz

CLKP

CLKM

Cf1

Cf2

Figure 8-3. Crystal Implementation

Note

The load capacitors, Cf1 and Cf2 in Figure 8-3, should be chosen such that Equation 1 is satisfied.

CL in the equation is the load specified by the crystal manufacturer. All discrete components used

to implement the oscillator circuit should be placed as close as possible to the associated oscillator

CLKP and CLKM pins.Note that Cf1 and Cf2 include the parasitic capacitances due to PCB routing.

Note

The board routing parasitics between CLKP/CLKM pins also need to be included in the estimates of

f 2

(1)

Table 8-5 lists the electrical characteristics of the clock crystal.

Table 8-5. Crystal Electrical Characteristics (Oscillator Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

Parallel resonance crystal frequency

MHz

Crystal load capacitance

ESR

Crystal ESR

Temperature range

Expected temperature range of operation

-40

125

℃

Frequency

tolererance

Crystal frequency tolerance(1) (2)

-100

100(3)

ppm

Drive level

200

μW

(1)

The crystal manufacturer's specification must satisfy this requirement.

(2)

Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.

(3)

For Ethernet operation, tighter specifications of less than 100 PPM frequency error is required. If the Ethernet interface is not used , a

PPM error up to 200 PPM can be tolerated.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM

is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-6

lists the electrical characteristics of the external clock signal.

AWR2944

SWRS273 – NOVEMBER 2021

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