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CDCDB803 Datasheet(PDF) 4 Page - Texas Instruments |
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CDCDB803 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 31 page  Table 5-1. Pin Functions (continued) PIN I/O TYPE(2) DESCRIPTION NAME NO. MANAGEMENT AND CONTROL (1) CKPWRGD_PD# 1 I, S, PD Clock Power Good and Power Down multi-function input pin with internal 180-kΩ pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. After PWRGD has been asserted high for the first time, the pin becomes a PD# pin and it controls power-down mode: LOW: Power-down mode, all output channels tri-stated. HIGH: Normal operation mode. OE0# 12 I, S, PD Output Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 0. HIGH: disable output channel 0. OE1# 18 I, S, PD Output Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 1. HIGH: disable output channel 1. OE2# 23 I, S, PD Output Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 2. HIGH: disable output channel 2. OE3# 24 I, S, PD Output Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 3. HIGH: disable output channel 3. OE4# 30 I, S, PD Output Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 4. HIGH: disable output channel 4. OE5# 31 I, S, PD Output Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 5. HIGH: disable output channel 5. OE6# 37 I, S, PD Output Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 6. HIGH: disable output channel 6. OE7# 41 I, S, PD Output Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 7. HIGH: disable output channel 7. SMBUS AND SMBUS ADDRESS SADR0 5 I, S, PU / PD SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction with pin 8 to set SMBus address. It has internal 120-kΩ pullup / pulldown network biasing to VDD/2 when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration input, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground. SMBDAT 6 I / O Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k. SMBCLK 7 I Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k. CDCDB803 SNAS820 – AUGUST 2021 www.ti.com 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: CDCDB803 |
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