8 Detailed Description

8.1 Overview

The CDCDB803 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict

performance requirements for PCIe Gen 1-5, QPI, UPI, SAS, and SATA reference clocks. The CDCDB803

allows buffering and replication of a single clock source to up to eight individual outputs in the LP-HCSL format.

The CDCDB803 also includes status and control registers accessible by an SMBus version 2.0 compliant

interface. The device integrates a large amount of external passive components to reduce overall system cost.

8.2 Functional Block Diagram

CLKIN_P

CLKIN_N

CK0_P

CK0_N

CK1_P

CK1_N

CK2_P

CK2_N

CK3_P

CK3_N

CK7_P

CK7_N

SMBDAT

SMBCLK

Glitch

Free

Output

Control

Logic

Control

Logic

CKPWRGD_PD#

OE[7:0]#

SADR0

SADR1

SMBWRTLOCK

8.3 Feature Description

8.3.1 Fail-Safe Input

The CDCDB803 is designed to support fail-safe input operation feature. This feature allows the user to drive the

for more information on the maximum input supported by the device.

8.3.2 Output Enable Control

The CDCDB803 uses SMBus and OE# to control the state of the output channels. The OE# pins control the

state of the output with the same number. For example, the OE5# pin controls the state of the CK5 output driver.

The SMBus registers may enable or disable the output when the corresponding OE# pin is held low.

8.3.3 SMBus

The CDCDB803 has an SMBus interface that is active only when CKPWRGD_PD# = 1. The SMBus allows

individual enable/disable of each output.

When CKPWRGD_PD# = 0, the SMBus pins are placed in a Hi-Z state, but all register settings are retained. The

8.3.3.1 SMBus Address Assignment

The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three

levels. This configuration allows the CDCDB803 to assume nine different SMBus addresses.

CDCDB803

SNAS820 – AUGUST 2021

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