9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The CDCDB803 is a fanout buffer that supports PCIe generation 4 and PCIe generation 5 REFCLK distribution.

It is used to distribute up to eight copies of a typically 100-MHz clock.

9.2 Typical Application

Figure 9-1 shows a CDCDB803 typical application. In this application, a clock generator provides a 100-MHz

reference to the CDCDB803 which then distributes that clock to PCIe endpoints. The clock generator may be a

discrete clock generator like the LMK03328 or it may be integrated in a larger component such as a Platform

Controller Hub (PCH) or application processor.

PCIe Gen 4-5

Clock

Generator

CDCDB803

8x LP-HSCL Output Buffer

SMBus

Control

OE#

Control

LP-HCSL

PCIe PHY

PCIe PHY

PCIe PHY

PCIe PHY

LP-HCSL

8

PCIe PHY

PCIe PHY

PCIe Device

Control Interface

Figure 9-1. Typical Application

9.2.1 Design Requirements

Consider a typical server motherboard application which must distribute a 100-MHz PCIe reference clock from

the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:

• Clock Input:

– 100-MHz LP-HCSL

• Clock Output:

– 2x 100-MHz to processors, LP-HCSL

– 3x 100-MHz to riser/retimer, LP-HCSL

– 3x 100-MHz to DDR memory controller, LP-HCSL

CDCDB803

SNAS820 – AUGUST 2021

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